FW82801IRQT28 View Datasheet(PDF) - Intel

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FW82801IRQT28

Intel® I/O Controller Hub 9 (ICH9) Family

Intel 

13.2

13.3

13.4

13.1.31 FDCAP—Feature Detection Capability ID

(LPC I/F—D31:F0) ................................................................................ 450

13.1.32 FDLEN—Feature Detection Capability Length

(LPC I/F—D31:F0) ................................................................................ 450

13.1.33FDVER—Feature Detection Version

(LPC I/F—D31:F0) ................................................................................ 450

13.1.34FDVCT—Feature Vector

(LPC I/F—D31:F0) ................................................................................ 451

13.1.35RCBA—Root Complex Base Address Register

(LPC I/F—D31:F0) ................................................................................ 451

DMA I/O Registers (LPC I/F—D31:F0) ................................................................ 452

13.2.1 DMABASE_CA—DMA Base and Current Address

Registers (LPC I/F—D31:F0) .................................................................. 453

13.2.2 DMABASE_CC—DMA Base and Current Count Registers

(LPC I/F—D31:F0) ................................................................................ 454

13.2.3 DMAMEM_LP—DMA Memory Low Page Registers

(LPC I/F—D31:F0) ................................................................................ 454

13.2.4 DMACMD—DMA Command Register (LPC I/F—D31:F0) .............................. 455

13.2.5 DMASTA—DMA Status Register (LPC I/F—D31:F0) .................................... 455

13.2.6 DMA_WRSMSK—DMA Write Single Mask Register

(LPC I/F—D31:F0) ................................................................................ 456

13.2.7 DMACH_MODE—DMA Channel Mode Register

(LPC I/F—D31:F0) ................................................................................ 457

13.2.8 DMA Clear Byte Pointer Register (LPC I/F—D31:F0) .................................. 458

13.2.9 DMA Master Clear Register (LPC I/F—D31:F0) .......................................... 458

13.2.10DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0) ........................ 458

13.2.11DMA_WRMSK—DMA Write All Mask Register

(LPC I/F—D31:F0) ................................................................................ 459

Timer I/O Registers (LPC I/F—D31:F0)............................................................... 460

13.3.1 TCW—Timer Control Word Register (LPC I/F—D31:F0) .............................. 461

13.3.2 RDBK_CMD—Read Back Command (LPC I/F—D31:F0)............................... 462

13.3.3 SBYTE_FMT—Interval Timer Status Byte Format Register

(LPC I/F—D31:F0) ................................................................................ 463

13.3.4 Counter Access Ports Register (LPC I/F—D31:F0) ..................................... 464

8259 Interrupt Controller (PIC) Registers

(LPC I/F—D31:F0) ........................................................................................... 465

13.4.1 Interrupt Controller I/O MAP (LPC I/F—D31:F0) ....................................... 465

13.4.2 ICW1—Initialization Command Word 1 Register

(LPC I/F—D31:F0) ................................................................................ 466

13.4.3 ICW2—Initialization Command Word 2 Register

(LPC I/F—D31:F0) ................................................................................ 467

13.4.4 ICW3—Master Controller Initialization Command

Word 3 Register (LPC I/F—D31:F0)......................................................... 468

13.4.5 ICW3—Slave Controller Initialization Command

Word 3 Register (LPC I/F—D31:F0)......................................................... 468

13.4.6 ICW4—Initialization Command Word 4 Register

(LPC I/F—D31:F0) ................................................................................ 469

13.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)

Register (LPC I/F—D31:F0).................................................................... 469

13.4.8 OCW2—Operational Control Word 2 Register

(LPC I/F—D31:F0) ................................................................................ 470

13.4.9 OCW3—Operational Control Word 3 Register

(LPC I/F—D31:F0) ................................................................................ 471

13.4.10ELCR1—Master Controller Edge/Level Triggered Register

(LPC I/F—D31:F0) ................................................................................ 472

13.4.11ELCR2—Slave Controller Edge/Level Triggered Register

(LPC I/F—D31:F0) ................................................................................ 473

Intel® I/O Controller Hub 9 (ICH9) Family Datasheet

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