W25Q32FVTCIF View Datasheet(PDF) - Winbond

Part Name

Description

View to exact match

W25Q32FVTCIF

3V 32M-Bit Serial Flash Memory

Winbond 

W25Q32FV

Figure 4c. Status Register-3

7.1.11 Write Protect Selection (WPS) – Volatile/Non-Volatile Writable

The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the device will

use the combination of CMP, SEC, TB, BP[2:0] bits to protect a specific area of the memory array. When

WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The

default value for all Individual Block Lock bits is 1 upon device power on or after reset.

7.1.12 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable

The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.

DRV1, DRV0

Driver Strength

0, 0

100%

0, 1

75%

1, 0

50%

1, 1

25% (default)

7.1.13 /HOLD or /RESET Pin Function (HOLD/RST) – Volatile/Non-Volatile Writable

The HOLD/RST bit is used to determine whether /HOLD or /RESET function should be implemented on

the hardware pin for 8-pin packages. When HOLD/RST=0 (factory default), the pin acts as /HOLD; when

HOLD/RST=1, the pin acts as /RESET. However, /HOLD or /RESET functions are only available when

QE=0. If QE is set to 1, the /HOLD and /RESET functions are disabled, the pin acts as a dedicated data

I/O pin.

- 19 -

Share Link: