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24502BVA View Datasheet(PDF) - Intersil

Part Name
Description
View to exact match
24502BVA
Intersil
Intersil Intersil
24502BVA Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
HM-6514
Timing Waveforms
(2) TAVQV
(7)
TAVEL
(8)
TELAX
A
VALID ADD
(6)
TEHEL
(2) TAVQY
E
HIGH Z
DQ
(1) TELQV
(3) TELQX
(17) TELEL
(5) TELEH
(7) TAVEL
NEXT ADD
(6)
TEHEL
(4) TEHQZ
VALID DATA OUT
HIGH Z
W
TIME
REFERENCE
TIME
REFERENCE
-1
0
1
2
3
4
5
-1
0
INPUTS
E
W
H
X
H
L
H
L
H
H
H
X
H
1
2
FIGURE 1. READ CYCLE
TRUTH TABLE
34
5
DATA I/O
A
DQ
FUNCTION
X
Z
Memory Disabled
V
Z
Cycle Begins, Addresses are Latched
X
X
Output Enabled
X
V
Output Valid
X
V
Read Accomplished
X
Z
Prepare for Next Cycle (Same as -1)
V
Z
Cycle Ends, Next Cycle Begins (Same as 0)
The address information is latched in the on-chip registers
on the falling edge of E (T = 0). Minimum address set up and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1) the output becomes
enabled, but data is not valid until during time (T = 2). W
must remain high throughout the read cycle. After the output
data has been read, E may return high (T = 3). This will dis-
able the output buffer and all inputs, and ready the RAM for
the next memory cycle (T = 4).
6-5
 

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