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24502BVA View Datasheet(PDF) - Intersil

Part Name
Description
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24502BVA
Intersil
Intersil Intersil
24502BVA Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
HM-6514
AC Electrical Specifications VCC = 5V ±10%; TTAA==-4-505ooCCtoto++8152o5CoC(H(MH-M65-61541S4-B9,-8H, MH-M65-61541B4--98,)HM-6514-9)
LIMITS
SYMBOL
PARAMETER
HM-6514S-9
MIN MAX
HM-6514B-9
MIN MAX
HM-6514-9
MIN MAX
TEST
UNITS CONDITIONS
(1) TELQV
Chip Enable Access Time
-
120
-
220
-
300
ns
(Notes 1, 3)
(2) TAVQV
Address Access Time
-
120
-
220
-
320
ns
(Notes 1, 3, 4)
(3) TELQX
Chip Enable Output Enable
5
-
5
-
5
-
Time
ns
(Notes 2, 3)
(4) TEHQZ
Chip Enable Output Disable
-
50
-
80
-
100
ns
(Notes 2, 3)
Time
(5) TELEH
Chip Enable Pulse Negative
120
-
200
-
300
-
Width
ns
(Notes 1, 3)
(6) TEHEL
Chip Enable Pulse Positive
50
-
90
-
120
-
Width
ns
(Notes 1, 3)
(7) TAVEL
Address Setup Time
0
-
20
-
20
-
ns
(Notes 1, 3)
(8) TELAX
Address Hold Time
40
-
50
-
50
-
ns
(Notes 1, 3)
(9) TWLWH Write Enable Pulse Width
120
-
200
-
300
-
ns
(Notes 1, 3)
(10) TWLEH
Chip Enable Write Pulse
Setup Time
120
-
200
-
300
-
ns
(Notes 1, 3)
(11) TELWH Chip Enable Write Pulse Hold 120
-
200
-
300
-
Time
ns
(Notes 1, 3)
(12) TDVWH Data Setup Time
50
-
120
-
200
-
ns
(Notes 1, 3)
(13) TWHDX Data Hold Time
0
-
0
-
0
-
ns
(Notes 1, 3)
(14) TWLDV Write Data Delay Time
70
-
80
-
100
-
ns
(Notes 1, 3)
(15) TWLEL
Early Output High-Z Time
0
-
0
-
0
-
ns
(Notes 1, 3)
(16) TEHWH Late Output High-Z Time
0
-
0
-
0
-
ns
(Notes 1, 3)
(17) TELEL
Read or Write Cycle Time
170
-
290
-
420
-
-
(Notes 1, 3)
NOTES:
1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. VCC = 4.5V and 5.5V.
4. TAVQV = TELQV + TAVEL.
6-4
 

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