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HN58X25128I View Datasheet(PDF) - Renesas Electronics

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HN58X25128I Datasheet PDF : 27 Pages
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HN58X25128I/HN58X25256I
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be
considered, depending on the state of write protect (W):
If write protect (W) is driven high, it is possible to write to the Status Register provided that the
Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.
If write protect (W) is driven low, it is not possible to write to the Status Register even if the
Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.
(Attempts to write to the Status Register are rejected, and are not accepted for execution). As a
consequence, all the data bytes in the memory area that are software protected (SPM) by the Block
Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:
By setting the Status Register Write Disable (SRWD) bit after driving write protect (W) low.
By driving write protect (W) low after setting the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull write protect (W) high.
If write protect (W) is permanently tied high, the Hardware Protected Mode (HPM) can never be activated,
and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register,
can be used.
Write Protected Block Size
Status register bits
BP1
BP0
0
0
0
1
1
0
1
1
Protected blocks
None
Upper quarter
Upper half
Whole memory
Array addresses protected
HN58X25256I
HN58X25128I
None
None
6000h 7FFFh
3000h 3FFFh
4000h 7FFFh
2000h 3FFFh
0000h 7FFFh
0000h 3FFFh
Rev.1.00, Jun.20.2003, page 22 of 27
 

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