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HN58X25128I View Datasheet(PDF) - Renesas Electronics

Part Name
Description
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HN58X25128I Datasheet PDF : 27 Pages
First Prev 21 22 23 24 25 26 27
HN58X25128I/HN58X25256I
Byte Write (WRITE) Sequence (Page)
VIH
5
VIL
9
VIH
VIL
VIH
C
VIL
VIH
D
VIL
Q
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
Instruction
16-Bit Address
Data Byte 1
15 14 13 3 2 1 0 7 6 5 4 3 2 1 0
High-Z
VIH
5
VIL
9
VIH
VIL
VIH
C
VIL
D
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
Data Byte N
765432107 6543210
6543210
Q
High-Z
Note: 1. Depending on the memory size, as shown in Address Range Bits table, the most significant
address bits are don’t care.
Data Protect
The protection features of the device are summarized in the following table. When the Status Register Write
Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status
Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction, regardless weather write protect (W) is driven high or low.
Rev.1.00, Jun.20.2003, page 21 of 27
 

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