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HN58X25128I(2005) View Datasheet(PDF) - Renesas Electronics

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HN58X25128I Datasheet PDF : 22 Pages
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HN58X25128I/HN58X25256I
AC Characteristics
Test Conditions
Input pules levels:
VIL = VCC × 0.2
VIH = VCC × 0.8
Input rise and fall time: 10 ns
Input and output timing reference levels: VCC × 0.3, VCC × 0.7
Output reference levels: VCC × 0.5
Output load: 100 pF
(Ta = 40 to +85°C, VCC = 2.5 V to 5.5 V)
Parameter
Symbol
Alt
Min
Max
Unit
Notes
Clock frequency
fC
fSCK
S active setup time
tSLCH
tCSS1
90
S not active setup time
tSHCH
tCSS2
90
S deselect time
tSHSL
tCS
90
S active hold time
tCHSH
tCSH
90
S not active hold time
tCHSL
90
Clock high time
tCH
tCLH
90
Clock low time
tCL
tCLL
90
Clock rise time
tCLCH
tRC
Clock fall time
tCHCL
tFC
Data in setup time
tDVCH
tDSU
20
Data in hold time
tCHDX
tDH
30
Clock low hold time after HOLD not active
tHHCH
70
Clock low hold time after HOLD active
tHLCH
40
Clock high setup time before HOLD active
tCHHL
60
Clock high setup time before HOLD not
tCHHH
60
active
5
MHz
ns
ns
ns
ns
ns
ns
1
ns
1
1
µs
2
1
µs
2
ns
ns
ns
ns
ns
ns
Output disable time
Clock low to output valid
Output hold time
Output rise time
Output fall time
HOLD high to output low-Z
HOLD low to output low-Z
Write time
Erase / Write Endurance
tSHQZ
tDIS
100
ns
2
tCLQV
tV
70
ns
tCLQX
tHO
0
ns
tQLQH
tRO
50
ns
2
tQHQL
tFO
50
ns
2
tHHQX
tLZ
50
ns
2
tHLQZ
tHZ
100
ns
2
tW
tWC
5
ms
106
cycles
3
Notes: 1. tCH + tCL 1/fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Value guaranteed by characterization, not 100% tested in products (Ta = 25°C).
Rev.3.00, Jul.06.2005, page 5 of 20
 

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