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W25Q80DVZPI View Datasheet(PDF) - Winbond

Part NameW25Q80DVZPI Winbond
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W25Q80DVZPI Datasheet PDF : 71 Pages
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4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program
or write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the
device. After power-up, /CS must transition from high to low before a new instruction will be accepted.
The /CS input must track the VCC supply level at power-up (see “Power-up Timing and Write inhibit
threshold” and figure 45). If needed, a pull-up resister on /CS can be used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25Q80DV support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register 2 to be
set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.
4.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status
Register Protect (SRP0) bits, a portion as small as 4KB sector or the entire memory array can be
hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad
I/O, the /WP pin function is not available since this pin is used for IO2.
4.4 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,
while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored
(don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be
useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the
QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is
used for IO3. See figure 1a and 1b for the pin configuration of Quad I/O operation.
4.5 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations.
Publication Release Date:July 21, 2015
Prelimry-Revision G
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The W25Q80DV (8M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 1µA for power-down. All devices are offered in space-saving packages.
The W25Q80DV array is organized into 4,096 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q80DV has 256 erasable sectors and 16 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.)
The W25Q80DV supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. A Hold pin, Write Protect pin and programmable write protection, with top, bottom or complement array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number.

● Family of SpiFlash Memories
   – W25Q80DV: 8M-bit/1M-byte (1,048,576)
   – 256-byte per programmable page
   – Standard SPI: CLK,/CS,DI,DO,/WP,/Hold
   – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
   – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
   – Uniform 4KB Sectors, 32KB & 64KB Blocks
● Highest Performance Serial Flash
   – 104MHz Dual/Quad SPI clocks
   – 208/416MHz equivalent Dual/Quad SPI
   – 50MB/S continuous data transfer rate
● Software and Hardware Write Protection
   – Write-Protect all or portion of memory
   – Enable/Disable protection with /WP pin
   – Top or bottom array protection
● Flexible Architecture with 4KB sectors
   – Uniform Sector/Block Erase (4/32/64-kbytes)
   – Program one to 256 bytes < 0.8ms
   – Erase/Program Suspend & Resume
   – More than 100,000 erase/write cycles
   – More than 20-year data retention
● Low Power, Wide Temperature Range
   – Single 2.7 to 3.6V supply
   – <1µA Power-down(typ.)
● Space Efficient Packaging(1):
   – 8-pin SOIC 150-mil/208mil, VSOP 150-mil
   – 8-pad WSON 6x5-mm, USON 2x3-mm
   – 8-pin PDIP 300-mil
   – 8-ball WLCSP
   – Contact Winbond for KGD and other options

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