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W25Q80DVZPI View Datasheet(PDF) - Winbond

Part NameW25Q80DVZPI Winbond
Winbond Winbond
Description3V 8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI
W25Q80DVZPI Datasheet PDF : 71 Pages
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W25Q80DV
Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy
clock are required prior to the data output. The Quad I/O dramatically reduces instruction overhead
allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable
bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.
Byte 1 Byte 2
Figure 14a. Fast Read Quad I/O Instruction Sequence (M[7:0] =FFh)
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Publication Release Date:July 21, 2015
Prelimry-Revision G
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GENERAL DESCRIPTION
The W25Q80DV (8M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 1µA for power-down. All devices are offered in space-saving packages.
The W25Q80DV array is organized into 4,096 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q80DV has 256 erasable sectors and 16 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.)
The W25Q80DV supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. A Hold pin, Write Protect pin and programmable write protection, with top, bottom or complement array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number.

FEATURES
● Family of SpiFlash Memories
   – W25Q80DV: 8M-bit/1M-byte (1,048,576)
   – 256-byte per programmable page
   – Standard SPI: CLK,/CS,DI,DO,/WP,/Hold
   – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
   – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
   – Uniform 4KB Sectors, 32KB & 64KB Blocks
● Highest Performance Serial Flash
   – 104MHz Dual/Quad SPI clocks
   – 208/416MHz equivalent Dual/Quad SPI
   – 50MB/S continuous data transfer rate
● Software and Hardware Write Protection
   – Write-Protect all or portion of memory
   – Enable/Disable protection with /WP pin
   – Top or bottom array protection
● Flexible Architecture with 4KB sectors
   – Uniform Sector/Block Erase (4/32/64-kbytes)
   – Program one to 256 bytes < 0.8ms
   – Erase/Program Suspend & Resume
   – More than 100,000 erase/write cycles
   – More than 20-year data retention
● Low Power, Wide Temperature Range
   – Single 2.7 to 3.6V supply
   – <1µA Power-down(typ.)
● Space Efficient Packaging(1):
   – 8-pin SOIC 150-mil/208mil, VSOP 150-mil
   – 8-pad WSON 6x5-mm, USON 2x3-mm
   – 8-pin PDIP 300-mil
   – 8-ball WLCSP
   – Contact Winbond for KGD and other options

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