W25Q80DVSNI View Datasheet(PDF) - Winbond
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W25Q80DVSNI Datasheet PDF : 71 Pages
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W25Q80DV
Table of Contents
1.
GENERAL DESCRIPTION ......................................................................................................... 5
2.
FEATURES ................................................................................................................................. 5
3.
PACKAGE TYPES AND PIN CONFIGURATIONS..................................................................... 6
3.1 Pin Configuration SOIC 150-MIL/208-mil AND VSOP 150-mil:...................................... 6
3.2 Pad Configuration WSON 6x5-mm, USON 2X3-mm...................................................... 6
3.3 Pin Configuration PDIP 300-mil ...................................................................................... 7
3.4 Pin Description SOIC/VSOP , WSON/USON & PDIP 300-mil ....................................... 7
3.5 Ball Configuration WLCSP.............................................................................................. 8
3.6 Ball Description WLCSP ................................................................................................. 8
4.
PIN DESCRIPTIONS .................................................................................................................. 9
4.1 Chip Select (/CS) ............................................................................................................ 9
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)............................... 9
4.3 Write Protect (/WP) ......................................................................................................... 9
4.4 HOLD (/HOLD)................................................................................................................ 9
4.5 Serial Clock (CLK) .......................................................................................................... 9
5.
BLOCK DIAGRAM .................................................................................................................... 10
6.
FUNCTIONAL DESCRIPTION.................................................................................................. 11
6.1 SPI OPERATIONS........................................................................................................ 11
Standard SPI Instructions ...............................................................................................11
Dual SPI Instructions ......................................................................................................11
Quad SPI Instructions .....................................................................................................11
Hold Function..................................................................................................................11
6.2 WRITE PROTECTION.................................................................................................. 12
Write Protect Features ....................................................................................................12
7.
CONTROL AND STATUS REGISTERS ................................................................................... 13
7.1 STATUS REGISTER .................................................................................................... 13
BUSY ..............................................................................................................................13
Write Enable Latch (WEL) ..............................................................................................13
Block Protect Bits (BP2, BP1, BP0) ................................................................................13
Top/Bottom Block Protect (TB) .......................................................................................13
Sector/Block Protect (SEC).............................................................................................13
Complement Protect (CMP)............................................................................................13
Status Register Protect (SRP1, SRP0) ...........................................................................14
Erase/Program Suspend Status (SUS)...........................................................................14
Security Register Lock Bits (LB3, LB2, LB1)...................................................................14
Quad Enable (QE) ........................................................................................................15
Status Register Memory Protection (CMP = 0) .............................................................16
Status Register Memory Protection (CMP = 1) .............................................................17
8.
INSTRUCTIONS ....................................................................................................................... 18
8.1 Manufacturer and Device Identification ........................................................................ 18
8.2 Instruction Set Table 1 (Standard SPI Instructions)(1) .................................................. 19
8.3 Instruction Set Table 2 (Dual SPI Instructions)............................................................. 20
8.4 Instruction Set Table 3 (Quad SPI Instructions) ........................................................... 20
8.5 Instruction Descriptions ................................................................................................ 22
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Publication Release Date:July 21, 2015
Preli mry-Revision G
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