datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

25Q80DVAIG View Datasheet(PDF) - Winbond

Part Name
Description
View to exact match
25Q80DVAIG Datasheet PDF : 71 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
W25Q80DV
Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO0, IO1, IO2, and IO3. A Quad enable of Status Register-2 must
be executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit
QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the
W25Q80DV at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC
Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address
as shown in figure 12. The dummy clocks allow the device's internal circuits additional time for setting
up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins
should be high-impedance prior to the falling edge of the first data out clock.
Figure 12. Fast Read Quad Output Instruction Sequence Diagram
- 29 -
Publication Release Date:July 21, 2015
Prelimry-Revision G
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]