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W25Q80DVSSI View Datasheet(PDF) - Winbond

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W25Q80DVSSI Datasheet PDF : 71 Pages
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W25Q80DV
Read Status Register-1 (05h) and Read Status Register-2 (35h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is
entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 or 35hfor
Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out
on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in figure 7. The
Status Register bits are shown in figure 3a and 3b and include the BUSY, WEL, BP2-BP0, TB, SEC,
SRP0, SRP1, QE, LB3-1, CMP and SUS bits (see Status Register section earlier in this datasheet).
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write
Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when
the cycle is complete and if the device can accept another instruction. The Status Register can be read
continuously, as shown in Figure 7. The instruction is completed by driving /CS high.
Figure 7. Read Status Register Instruction Sequence Diagram
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Publication Release Date:July 21, 2015
Prelimry-Revision G
 

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