25Q80DVAIG View Datasheet(PDF) - Winbond

Part Name

Description

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25Q80DVAIG

3V 8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

Winbond 

W25Q80DV

Write Disable (04h)

The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register

to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into

the DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and

upon completion of the Write Status Register. Erase/Program Security Registers, Page Program, Quad

Page Program, Sector Erase, Block Erase and Chip Erase instructions. Write Disable instruction can

also be used to invalidate the Write Enable for Volatile Status Register instruction

/CS

CLK

Mode 3

Mode 0

DI

(IO0)

DO

(IO1)

0 1 2 3 4 5 6 7 Mode 3

Mode 0

Instruction (04h)

High Impedance

/CS

CLK

IO0

Mode 3

Mode 0

01

Instruction

04h

Mode 3

Mode 0

IO1

IO2

IO3

Figure 6. Write Disable Instruction Sequence Diagram

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Publication Release Date:July 21, 2015

Prelimry-Revision G

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