W25Q80DVSSI View Datasheet(PDF) - Winbond

Part Name

Description

View to exact match

W25Q80DVSSI

3V 8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

Winbond 

W25Q80DV

8. INSTRUCTIONS

The instruction set of the W25Q80DV consists of 34 basic instructions that are fully controlled through

the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip Select

(/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input

is sampled on the rising edge of clock with most significant bit (MSB) first.

Instructions vary in length from a single byte to several bytes and may be followed by address bytes,

data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed

with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in

figures 4 through 39. All read instructions can be completed after any clocked bit. However, all

instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a full

8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects the

device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when

the Status Register is being written, all instructions except for Read Status Register will be ignored until

the program or erase cycle has completed.

8.1 Manufacturer and Device Identification

MANUFACTURER ID

(MF7-MF0)

Winbond Serial Flash

EFh

Device ID

Instruction

W25Q80DV

(ID7-ID0)

ABh, 90h, 92h, 94h

13h

(ID15-ID0)

9Fh

4014h

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Publication Release Date:July 21, 2015

Prelimry-Revision G

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