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W25Q80DVSNI View Datasheet(PDF) - Winbond

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Description
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W25Q80DVSNI Datasheet PDF : 71 Pages
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W25Q80DV
Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
operation. When the QE bit is set to a 0 state (factory default for part numbers with ordering options
“IG”), the /WP pin and /HOLD are enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins
are enabled, and /WP and /HOLD functions are disabled.
WARNING: The QE bit should never be set to a 1 during standard SPI or Dual SPI operation if the /WP or /HOLD pins are
tied directly to the power supply or ground.
S7 S6 S5 S4 SS3 SS2 SS1 SS0
SRP0 SEC
TB
BP2
BP 1 BP0 WEL BUSY
STATUS REGISTER PROTECT0
(Non-volatile)
SECTOR PROTECT
(Non-volatile)
TOP/BOTTOM PROTECT
(Non-volatile)
BLOCK PROTECT BITS
(Non-volatile)
WRITE ENABLE LATCH
ERASE/WRITE IN PROGRESS
(volatile)
Figure3a. Status Register-1
S15 S14 S13 S12 S11 S10 S9 S8
SUS CMP LB3 LB2 LB1 (R) QE SRP1
Suspend Status
(Status-Only)
Complement Protect
(Volatile/Non-Volatile Writable)
Security Register Lock Bits
(Volatile/Non-Volatile OTP Writable)
Reserved
Quad Enable
(Volatile/Non-Volatile Writable)
Status Register Protect 1
(Volatile/Non-Volatile Writable)
Figure3b. Status Register-2
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Publication Release Date:July 21, 2015
Prelimry-Revision G
 

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