datasheetbank_Logo    Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :

W25Q80DVZPI View Datasheet(PDF) - Winbond

Part NameW25Q80DVZPI Winbond
Winbond Winbond
W25Q80DVZPI Datasheet PDF : 71 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
For instance, when CMP=0, a top 4KB sector can be protected while the rest of the array is not; when
CMP=1, the top 4KB sector will become unprotected while the rest of the array become read-only.
Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0.
Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register
(S8 and S7). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable (OTP) protection.
/WP pin has no control. The Status register can be written
to after a Write Enable instruction, WEL=1. [Factory
When /WP pin is low the Status Register locked and can
not be written to.
Hardware When /WP pin is high the Status register is unlocked and
Unprotected can be written to after a Write Enable instruction, WEL=1.
Power Supply Status Register is protected and can not be written to
Lock-Down again until the next power-down, power-up cycle.(1)
One Time Status Register is permanently protected and can not be
Program(2) written to.
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available upon special order. Please contact Winbond for details.
Erase/Program Suspend Status (SUS)
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a
Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume
(7Ah) instruction as well as a power-down, power-up cycle.
Security Register Lock Bits (LB3, LB2, LB1)
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The
default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the
Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-Byte Security Register will become read-only permanently.
- 14 -
Publication Release Date:July 21, 2015
Prelimry-Revision G
Direct download click here

The W25Q80DV (8M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 1µA for power-down. All devices are offered in space-saving packages.
The W25Q80DV array is organized into 4,096 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q80DV has 256 erasable sectors and 16 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.)
The W25Q80DV supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. A Hold pin, Write Protect pin and programmable write protection, with top, bottom or complement array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number.

● Family of SpiFlash Memories
   – W25Q80DV: 8M-bit/1M-byte (1,048,576)
   – 256-byte per programmable page
   – Standard SPI: CLK,/CS,DI,DO,/WP,/Hold
   – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
   – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
   – Uniform 4KB Sectors, 32KB & 64KB Blocks
● Highest Performance Serial Flash
   – 104MHz Dual/Quad SPI clocks
   – 208/416MHz equivalent Dual/Quad SPI
   – 50MB/S continuous data transfer rate
● Software and Hardware Write Protection
   – Write-Protect all or portion of memory
   – Enable/Disable protection with /WP pin
   – Top or bottom array protection
● Flexible Architecture with 4KB sectors
   – Uniform Sector/Block Erase (4/32/64-kbytes)
   – Program one to 256 bytes < 0.8ms
   – Erase/Program Suspend & Resume
   – More than 100,000 erase/write cycles
   – More than 20-year data retention
● Low Power, Wide Temperature Range
   – Single 2.7 to 3.6V supply
   – <1µA Power-down(typ.)
● Space Efficient Packaging(1):
   – 8-pin SOIC 150-mil/208mil, VSOP 150-mil
   – 8-pad WSON 6x5-mm, USON 2x3-mm
   – 8-pin PDIP 300-mil
   – 8-ball WLCSP
   – Contact Winbond for KGD and other options

Share Link : Winbond
@ 2014 - 2018  [ Home ] [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]