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W25Q80DVZPI View Datasheet(PDF) - Winbond

Part NameDescriptionManufacturer
W25Q80DVZPI 3V 8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI Winbond
Winbond Winbond
W25Q80DVZPI Datasheet PDF : 71 Pages
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W25Q80DV
For instance, when CMP=0, a top 4KB sector can be protected while the rest of the array is not; when
CMP=1, the top 4KB sector will become unprotected while the rest of the array become read-only.
Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0.
Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register
(S8 and S7). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable (OTP) protection.
SRP1 SRP0 /WP
Status
Register
Description
0
0
X
Software
Protection
/WP pin has no control. The Status register can be written
to after a Write Enable instruction, WEL=1. [Factory
Default]
0
1
0
Hardware
Protected
When /WP pin is low the Status Register locked and can
not be written to.
0
1
1
Hardware When /WP pin is high the Status register is unlocked and
Unprotected can be written to after a Write Enable instruction, WEL=1.
1
0
X
Power Supply Status Register is protected and can not be written to
Lock-Down again until the next power-down, power-up cycle.(1)
1
1
X
One Time Status Register is permanently protected and can not be
Program(2) written to.
Note:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available upon special order. Please contact Winbond for details.
Erase/Program Suspend Status (SUS)
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a
Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume
(7Ah) instruction as well as a power-down, power-up cycle.
Security Register Lock Bits (LB3, LB2, LB1)
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The
default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the
Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-Byte Security Register will become read-only permanently.
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Publication Release Date:July 21, 2015
Prelimry-Revision G
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