W25Q80DVZPI View Datasheet(PDF) - Winbond

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W25Q80DVZPI

3V 8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

Winbond 

W25Q80DV

To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate

on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the

/HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on

the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the

/HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial

Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored.

The Chip Select (/CS) signal should be kept active low for the full duration of the /HOLD operation to

avoid resetting the internal logic state of the device.

6.2 WRITE PROTECTION

Applications that use non-volatile memory must take into consideration the possibility of noise and other

adverse system conditions that may compromise data integrity. To address this concern, the

W25Q80DV provide several means to protect the data from inadvertent writes.

Write Protect Features

 Device resets when VCC is below threshold

 Time delay write disable after Power-up

 Write enable/disable instructions

 Automatic write disable after erase or program

 Software and Hardware (/WP pin) write protection using Status Register

 Write Protection using Power-down instruction

 Lock Down write protection until next power-up

 One Time Program (OTP) write protection*

* Note: This feature is available upon special order. Please contact Winbond for details.

Upon power-up or at power-down, the W25Q80DV will maintain a reset condition while VCC is below

the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 45). While reset, all

operations are disabled and no instructions are recognized. During power-up and after the VCC voltage

exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW.

This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write

Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at

power-up until the VCC-min level and tVSL time delay is reached. If needed, a pull-up resister on /CS

can be used to accomplish this.

After power-up the device is automatically placed in a write-disabled state with the Status Register Write

Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program,

Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After

completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared

to a write-disabled state of 0.

Software controlled write protection is facilitated using the Write Status Register instruction and setting

the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC,TB, BP2, BP1 and BP0) bits.

These settings allow a portion as small as 4KB sector or the entire memory array to be configured as

read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be

enabled or disabled under hardware control. See Status Register section for further information.

Additionally, the Power-down instruction offers an extra level of write protection as all instructions are

ignored except for the Release Power-down instruction.

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Publication Release Date:July 21, 2015

Prelimry-Revision G

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