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25Q64FVAIF View Datasheet(PDF) - Winbond

Part Name25Q64FVAIF Winbond
Winbond Winbond
Description3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI
25Q64FVAIF Datasheet PDF : 89 Pages
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W25Q64FV
6.2.18 Octal Word Read Quad I/O (E3h)
The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are
not required, which further reduces the instruction overhead allowing even faster random access for code
execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal Word
Read Quad I/O Instruction.
Octal Word Read Quad I/O with “Continuous Read Mode”
The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 17a. The
upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through
the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t
care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out
clock.
If the “Continuous Read Modebits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS
is raised and then lowered) does not require the E3h instruction code, as shown in Figure 17b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered
after /CS is asserted low. If the “Continuous Read Modebits M5-4 do not equal to (1,0), the next
instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to
normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4
= 1 and return the device to normal operation.
/CS
CLK
Mode 3
Mode 0
IO0
IO1
IO2
IO3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Instruction (E3h)
A23-16 A15-8
A7-0
M7-0
IOs switch from
Input to Output
20 16 12 8 4 0 4 0 4 0 4 0 4 0 4
21 17 13 9 5 1 5 1 5 1 5 1 5 1 5
22 18 14 10 6 2 6 2 6 2 6 2 6 2 6
23 19 15 11 7 3 7 3 7 3 7 3 7 3 7
Byte 1 Byte 2 Byte 3 Byte 4
Figure 17a. Octal Word Read Quad I/O Instruction (Initial instruction or previous M5-4 10, SPI Mode only)
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Publication Release Date: October 07, 2013
Revision L
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GENERAL DESCRIPTION
The W25Q64FV (64M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power-down. All devices are offered in space saving packages.

 

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