25Q64FVBIG View Datasheet(PDF) - Winbond

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25Q64FVBIG

3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

Winbond 

W25Q64FV

6.2.17 Word Read Quad I/O (E7h)

The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except

that the lowest Address bit (A0) must equal 0 and only two Dummy clock are required prior to the data

output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code

execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to

enable the Word Read Quad I/O Instruction.

Word Read Quad I/O with “Continuous Read Mode”

The Word Read Quad I/O instruction can further reduce instruction overhead through setting the

“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 16a. The

upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the

inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care

(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS

is raised and then lowered) does not require the E7h instruction code, as shown in Figure 16b. This

reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered

after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next

instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to

normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4

= 1 and return the device to normal operation.

/CS

CLK

Mode 3

Mode 0

IO0

IO1

IO2

IO3

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Instruction (E7h)

A23-16 A15-8

A7-0

M7-0 Dummy

IOs switch from

Input to Output

20 16 12 8 4 0 4 0

40404

21 17 13 9 5 1 5 1

51515

22 18 14 10 6 2 6 2

62626

23 19 15 11 7 3 7 3

73

Byte 1

73

Byte 2

7

Byte 3

Figure 16a. Word Read Quad I/O Instruction (Initial instruction or previous M5-4  10, SPI Mode only)

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Publication Release Date: October 07, 2013

Revision L

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