datasheetbank_Logo    Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :

W25Q64FVSFIQ View Datasheet(PDF) - Winbond

Part NameW25Q64FVSFIQ Winbond
Winbond Winbond
W25Q64FVSFIQ Datasheet PDF : 89 Pages
First Prev 31 32 33 34 35 36 37 38 39 40 Next Last
6.2.16 Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy
clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction
overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad
Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 15a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Modebits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS
is raised and then lowered) does not require the EBh instruction code, as shown in Figure 15b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered
after /CS is asserted low. If the “Continuous Read Modebits M5-4 do not equal to (1,0), the next
instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to
normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4
= 1 and return the device to normal operation.
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction (EBh)
A23-16 A15-8
M7-0 Dummy Dummy
IOs switch from
Input to Output
20 16 12 8 4 0 4 0
21 17 13 9 5 1 5 1
22 18 14 10 6 2 6 2
23 19 15 11 7 3 7 3
Byte 1
Byte 2
Byte 3
Figure 15a. Fast Read Quad I/O Instruction (Initial instruction or previous M5-410, SPI Mode)
- 36 -
Direct download click here

The W25Q64FV (64M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power-down. All devices are offered in space saving packages.


Share Link : Winbond
@ 2014 - 2018  [ Home ] [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]