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W25Q64FVSFIQ View Datasheet(PDF) - Winbond

Part NameW25Q64FVSFIQ Winbond
Winbond Winbond
Description3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI
W25Q64FVSFIQ Datasheet PDF : 89 Pages
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W25Q64FV
6.2.15 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to
input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 14a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Modebits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS
is raised and then lowered) does not require the BBh instruction code, as shown in Figure 14b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered
after /CS is asserted low. If the “Continuous Read Modebits M5-4 do not equal to (1,0), the next
instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to
normal operation. It is recommended to input FFFFh on IO0 for the next instruction (16 clocks), to ensure
M4 = 1 and return the device to normal operation.
/CS
CLK
Mode 3
Mode 0
DI
(IO0)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction (BBh)
A23-16
A15-8
A7-0
M7-0
22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0
DO
(IO1)
/CS
CLK
DI
(IO0)
* = MSB
23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1
*
*
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
IOs switch from
Input to Output
064206420642064206
DO
(IO1)
175317531753175317
* Byte 1
* Byte 2
* Byte 3
* Byte 4
Figure 14a. Fast Read Dual I/O Instruction (Initial instruction or previous M5-4 10, SPI Mode only)
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GENERAL DESCRIPTION
The W25Q64FV (64M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power-down. All devices are offered in space saving packages.

 

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