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W25Q64FVSFIQ View Datasheet(PDF) - Winbond

Part NameDescriptionManufacturer
W25Q64FVSFIQ 3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI Winbond
Winbond Winbond
W25Q64FVSFIQ Datasheet PDF : 89 Pages
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W25Q64FV
6.2.13 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins; IO0 and IO1. This allows data to be transferred from the W25Q64FV at
twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly
downloading code from Flash to RAM upon power-up or for applications that cache code-segments to
RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in Figure 12. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy clocks
is “don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data
out clock.
/CS
CLK
DI
(IO0)
DO
(IO1)
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Instruction (3Bh)
24-Bit Address
23 22 21
*
High Impedance
3210
* = MSB
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Clocks
IO0 switches from
Input to Output
0
64206420642064206
High Impedance
75317531753175317
* Data Out 1
* Data Out 2
* Data Out 3
* Data Out 4
Figure 12. Fast Read Dual Output Instruction (SPI Mode only)
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