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W25Q64FVSFIQ View Datasheet(PDF) - Winbond

Part NameW25Q64FVSFIQ Winbond
Winbond Winbond
Description3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI
W25Q64FVSFIQ Datasheet PDF : 89 Pages
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W25Q64FV
6.2.8 Write Disable (04h)
The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the
DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page
Program, Sector Erase, Block Erase, Chip Erase and Reset instructions.
/CS
CLK
Mode 3
Mode 0
DI
(IO0)
DO
(IO1)
01234567
Instruction (04h)
Mode 3
Mode 0
High Impedance
/CS
CLK
IO0
Mode 3
Mode 0
01
Instruction
04h
Mode 3
Mode 0
IO1
IO2
IO3
Figure 7. Write Disable Instruction for SPI Mode (left) or QPI Mode (right)
6.2.9 Read Status Register-1 (05h) and Read Status Register-2 (35h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is
entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 or 35hfor
Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on
the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 8. The Status
Register bits are shown in Figure 4a and 4b and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP0,
SRP1, QE, LB3-0, CMP and SUS bits (see Status Register section earlier in this datasheet).
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write
Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when
the cycle is complete and if the device can accept another instruction. The Status Register can be read
continuously, as shown in Figure 8. The instruction is completed by driving /CS high.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 3
0
Mode 0
* = MSB
123456
Instruction (05h or 35h)
High Impedance
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Status Register 1 or 2 out
Status Register 1 or 2 out
76543210765432107
*
*
Figure 8a. Read Status Register Instruction (SPI Mode)
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GENERAL DESCRIPTION
The W25Q64FV (64M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power-down. All devices are offered in space saving packages.

 

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