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W25Q64FVSFIQ View Datasheet(PDF) - Winbond

Part NameDescriptionManufacturer
W25Q64FVSFIQ 3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI Winbond
Winbond Winbond
W25Q64FVSFIQ Datasheet PDF : 89 Pages
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W25Q64FV
6.1.10 Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
and QPI operation. When the QE bit is set to a 0 state (factory default for part number with ordering
options “IG” and “IF”), the /WP pin and /HOLD are enabled. When the QE bit is set to a 1(factory default
for Quad Enabled part numbers with ordering option “IQ”), the Quad IO2 and IO3 pins are enabled, and
/WP and /HOLD functions are disabled.
QE bit is required to be set to a 1 before issuing an “Enable QPI (38h)” to switch the device from
Standard/Dual/Quad SPI to QPI, otherwise the command will be ignored. When the device is in QPI
mode, QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot change QE bit
from a “1” to a “0”.
WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during
standard SPI or Dual SPI operation, the QE bit should never be set to a 1.
S7 S6 S5 S4 S3 S2 S1 S0
STATUS REGISTER PROTECT 0
(non-volatile)
SECTOR PROTECT
(non-volatile)
TOP/BOTTOM PROTECT
(non-volatile)
BLOCK PROTECT BITS
(non-volatile)
WRITE ENABLE LATCH
ERASE/WRITE IN PROGRESS
SRP0 SEC TB BP2 BP1 BP0 WEL BUSY
Figure 4a. Status Register-1
S15 S14 S13 S12 S11 S10 S9 S8
SUS CMP LB3 LB2 LB1 (R) QE SRP1
SUSPEND STATUS
COMPLEMENT PROTECT
(non-volatile)
SECURITY REGISTER LOCK BITS
(non-volatile OTP)
RESERVED
QUAD ENABLE
(non-volatile)
STATUS REGISTER PROTECT 1
(non-volatile)
Figure 4b. Status Register-2
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Publication Release Date: October 07, 2013
Revision L
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