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CLC2011 View Datasheet(PDF) - Exar Corporation

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CLC2011 Datasheet PDF : 16 Pages
First Prev 11 12 13 14 15 16
Data Sheet
Input
+
-
Rf
Rg
Rs
Output
CL
RL
Figure 6. Addition of RS for Driving Capacitive Loads
Table 1 provides the recommended RS for various capacitive
loads. The recommended RS values result in approximately
<1dB peaking in the frequency response. The Frequency
Response vs. CL plot, on page 6, illustrates the response
of the CLCx011.
3
2.5
G=5
2
1.5
1
0.5
Output
0
Input
-0.5
-1
-1.5
-2
-2.5
-3
0
2
4
6
8 10 12 14 16 18 20
Time (us)
Figure 7. Overdrive Recovery
CL (pF)
10pF
20pF
50pF
100pF
RS (Ω)
0
0
0
100
-3dB BW (kHz)
2.2
2.4
2.5
2
Table 1: Recommended RS vs. CL
For a given load capacitance, adjust RS to optimize the
tradeoff between settling time and bandwidth. In general,
reducing RS will increase bandwidth at the expense of
additional overshoot and ringing.
Overdrive Recovery
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for
the amplifier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The CLCx011 will typically recover in less
than 50ns from an overdrive condition. Figure 7 shows the
CLC2011 in an overdriven condition.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
an aid in device testing and characterization. Follow the
steps below as a basis for high frequency layout:
▪▪Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
▪▪Place the 6.8µF capacitor within 0.75 inches of the power pin
▪▪Place the 0.1µF capacitor within 0.1 inches of the power pin
▪▪Remove the ground plane under and around the part,
especially near the input and output pins to reduce
parasitic capacitance
▪▪Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board #
Products
CEB006
CLC2011 in SOIC
CEB010
CLC2011 in MSOP
CEB018
CLC4011 in SOIC
CEB017
CLC4011 in TSSOP
©2009-2013 Exar Corporation
11/16
Rev 1C
 

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