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ADC-318A View Datasheet(PDF) - DATEL Data Acquisition products

Part Name
Description
View to exact match
ADC-318A
Datel
DATEL Data Acquisition products  Datel
ADC-318A Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
®
®
ADC-318, ADC-318A
POWER REQUIREMENTS (cont.)
Power Dissipation
ADC-318
ADC-318A
680
780
980
mW
570
790
960
mW
PARAMETERS
Operating Temp. Range, Case
ADC-318, 318A
Thermal Impedance
θja 1 2
Storage Temperature Range
Package Type
Weight
–20
+75
°C
62.5
°C/Watt
–65
+150
°C
48-pin, plastic QFP
0.25 ounces (0.7 grams)
Footnotes:
ΠVIN = +3V +0.07Vrms
 VIH = DGND3–0.8V
VIL = DGND3–1.6V
Ž VIH = 3.5V
VIL = 0.2V
 TTL, 0.8 to 2.0V, CL = 5pF
 DMUX Mode, CL = 5pF; FC = Clock
frequency
‘ Straight Mode, CL = 5pF
’ CL = 5pF
“ VIN = FS, DMUX mode
” VIN = FS, DMUX mode, Error >16LSB
• VIN = FS, Straight mode, Error >16LSB
11 "Times Per Sample"
12 Mounted on 50x50mm, 1.6mm thick
glass fiber base epoxy board
TECHNICAL NOTES
1. The ADC-318 and ADC-318A are ultra high speed full flash
A/D converters that have 120MHz and 140MHz sampling
rates respectively. The ADC-318 and ADC-318A are fully
interchangeable products with the exception of their
sampling rates. Their inputs are TTL, ECL and PECL
compatible and their outputs are TTL compatible. Obtaining
fully specified performance from the ADC-318 and ADC-
5V(A)
10µF
+
10µH
5V(D)
10µF
+
318A requires that the characteristic impedance of all input/
output logic and analog input lines be properly matched.
2. Power supply lines and grounding may effect the perfor-
mance of the ADC-318 and ADC-318A. Separate and
substantial AGND and DGND ground planes are required.
These grounds have to be connected to one earth point
underneath the device. There are three digital grounds,
DGND1 (pin 29), DGND2 (pins 20, 32, 41) and DGND3 (pin
12). These DGND 's are separated internally. DGND1 and
DGND2 are always connected externally but DGND3 shall
be connected differently depending on whether the single or
dual power supply mode is used, as explained later.
The ADC-318 and ADC-318A have separate +AVs and
+DVs pins. It is recommended that both +AVs and +DVs be
powered from a single source. Other external digital circuits
must be powered with a separate +DVs. Layouts of +AVs
and +DVs lines must be separated like the GND lines to
avoid mutual interference and are connected to a point
through an LC filter. There are two digital supplies +DVs1
(pin 30) and +DVs2 (pins 19, 31, 42). These are also
separated internally. These must be tied together outside
while in use. Bypassing all power lines with a 0.1uF ceramic
chip capacitor and the use of multilayered PC boards is
recommended.
3. The analog input terminal (pin 6) has 21pF of input capaci-
tance. The input signal has to be given via a buffer amplifier
which has enough driving power. Make lead wires as short
as possible and use chip resistors and capacitors to avoid
parasitic capacitance and inductance.
4. The use of a buffer amplifier and bypass capacitors is also
recommended on the reference input terminals VRT (pin 11)
and VRB (pin 2). The analog input range is determined by
5V(A)
10µF
+
10µH
5V(D)
10µF
+
VRB
+2V
10µF
ANALOG IN
+2V to +4V
VRT
+4V
TTL
10µF
A/D CLOCK
PECL
58
12 19 30 31 42
MSB
2
+
40 A BIT 1
39 A BIT 2
38 A BIT 3
37 A BIT 4
36 A BIT 5
35 A BIT 6
4
34 A BIT 7
6
33 A BIT 8
7
LSB
MSB
9
28 B BIT 1
11
+
ADC-318
ADC-318A
27 B BIT 2
26 B BIT 3
25 B BIT 4
24 B BIT 5
23 B BIT 6
15
22 B BIT 7
13
21 B BIT 8
14
LSB
48
43 TTL
CLOCK OUT
47
44
46
45
3 10
1 20 29 32 41
5V(D)
5V(D)
VRB
+2V
10µF
ANALOG IN
+2V to +4V
VRT
+4V
10µF
A/D CLOCK
ECL
A/D CLOCK
58
19 30 31 42
MSB
2
+
40 A BIT 1
39 A BIT 2
38 A BIT 3
37 A BIT 4
36 A BIT 5
35 A BIT 6
4
34 A BIT 7
6
33 A BIT 8
7
LSB
MSB
9
28 B BIT 1
11
+
ADC-318
ADC-318A
27 B BIT 2
26 B BIT 3
25 B BIT 4
24 B BIT 5
23 B BIT 6
15
22 B BIT 7
13
21 B BIT 8
14
LSB
48
43 TTL
CLOCK OUT
47
44
46
45
3 10 1 12 20 29 32 41
5V(D)
+
5V(D)
10µF
5V(D)
Figure 2-1: One Power Supply Operation (TTL, PECL)
Figure 2-2: Two Power Supply Operation (ECL)
Note: All capacitors not otherwise designated are 0.1µF
3
 

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