NXP Semiconductors
TDA5051A
Home automation modem
11.2 Timing diagrams
90 % VDD
VDD
CLK_OUT
not defined
clock stable
DATA_IN(1)
HIGH
TX_OUT
td(pu)(TX)
002aaf046
(1) DATA_IN is an edge-sensitive input and must be HIGH before starting a transmission.
Fig 10. Timing diagram during power-up in Transmission mode
90 % VDD
VDD
CLK_OUT
not defined
clock stable
RX_IN
DATA_OUT
not defined
HIGH
td(pu)(RX)
Fig 11. Timing diagram during power-up in Reception mode
td(dem)(h)
002aaf047
PD
DATA_IN
TX_OUT
td(pd)(TX)
normal operation
wrong operation
Fig 12. Power-down sequence in Transmission mode
TX_OUT
delayed by PD
002aaf048
TDA5051A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 13 January 2011
© NXP B.V. 2011. All rights reserved.
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