SRV05-4MR6 View Datasheet(PDF) - ON Semiconductor
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SRV05-4MR6 Datasheet PDF : 9 Pages
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SRV05−4MR6
Power
Supply
VCC
IESDpos
Protected Data Line
Device
D1 IESDpos
IESDneg
D2
IESDneg
VF + VCC
−VF
Looking at the figure above, it can be seen that when a
positive ESD condition occurs, diode D1 will be forward
biased while diode D2 will be forward biased when a
negative ESD condition occurs. For slower transient
conditions, this system may be approximated as follows:
For positive pulse conditions:
Vc = VCC + VfD1
For negative pulse conditions:
Vc = −VfD2
ESD events can have rise times on the order of some
number of nanoseconds. Under these conditions, the effect
of parasitic inductance must be considered. A pictorial
representation of this is shown below.
Power
Supply
VCC
Protected
Device Data Line
IESDpos
D1 IESDpos
IESDneg
D2 VC = VCC + Vf + (L diESD/dt)
IESDneg
VC = −Vf − (L diESD/dt)
An approximation of the clamping voltage for these fast
transients would be:
For positive pulse conditions:
Vc = VCC + Vf + (L diESD/dt)
For negative pulse conditions:
Vc = −Vf – (L diESD/dt)
As shown in the formulas, the clamping voltage (Vc) not
only depends on the Vf of the steering diodes but also on the
L diESD/dt factor. A relatively small trace inductance can
result in hundreds of volts appearing on the supply rail. This
endangers both the power supply and anything attached to
that rail. This highlights the importance of good board
layout. Taking care to minimize the effects of parasitic
inductance will provide significant benefits in transient
immunity.
Even with good board layout, some disadvantages are still
present when discrete diodes are used to suppress ESD
events across datalines and the supply rail. Discrete diodes
with good transient power capability will have larger die and
therefore higher capacitance. This capacitance becomes
problematic as transmission frequencies increase. Reducing
capacitance generally requires reducing die size. These
small die will have higher forward voltage characteristics at
typical ESD transient current levels. This voltage combined
with the smaller die can result in device failure.
The ON Semiconductor SRV05−4MR6 was developed to
overcome the disadvantages encountered when using
discrete diodes for ESD protection. This device integrates a
TVS diode within a network of steering diodes.
D1
D3
D5
D7
D2
D4
D6
D8
0
Figure 8. SRV05−4MR6 Equivalent Circuit
During an ESD condition, the ESD current will be driven
to ground through the TVS diode as shown below.
Power
Supply
VCC
Protected
Device Data Line
D1 IESDpos
D2
The resulting clamping voltage on the protected IC will
be:
Vc = VF + VTVS.
The clamping voltage of the TVS diode is provided in
Figure 7 and depends on the magnitude of the ESD current.
The steering diodes are fast switching devices with unique
forward voltage and low capacitance characteristics.
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