M4-192/96-12VI View Datasheet(PDF) - Lattice Semiconductor

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M4-192/96-12VI

MACH 4 CPLD Family High Performance E2CMOS® In-System Programmable Logic

Lattice Semiconductor 

IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY

All MACH 4 devices, except the M4(LV)-128N/64, have boundary scan cells and are compliant

to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the

device is mounted through a serial scan path that can access all critical logic nodes. Internal

registers are linked internally, allowing test data to be shifted in and loaded directly onto test

nodes, or test node data to be captured and shifted out for verification. In addition, these devices

can be linked into a board-level serial scan path for more complete board-level testing.

IEEE 1149.1-COMPLIANT IN-SYSTEM PROGRAMMING

Programming devices in-system provides a number of significant benefits including: rapid

prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications.

All MACH 4 devices provide In-System Programming (ISP) capability through their Boundary

ScanTest Access Ports. This capability has been implemented in a manner that ensures that the

port remains compliant to the IEEE 1149.1 standard. By using IEEE 1149.1 as the communication

interface through which ISP is achieved, customers get the benefit of a standard, well-defined

interface.

MACH 4 devices can be programmed across the commercial temperature and voltage range. The

PC-based LatticePRO software facilitates in-system programming of MACH 4 devices. LatticePRO

takes the JEDEC file output produced by the design implementation software, along with

information about the JTAG chain, and creates a set of vectors that are used to drive the JTAG

chain. LatticePRO software can use these vectors to drive a JTAG chain via the parallel port of a

PC. Alternatively, LatticePRO software can output files in formats understood by common

automated test equipment. This equpment can then be used to program MACH 4 devices during

the testing of a circuit board.

PCI COMPLIANT

MACH 4 devices in the -7/-10/-12 speed grades are compliant with the PCI Local Bus

Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are

fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition

to clamp the inputs as they rise above VCC because of their 5-V input tolerant feature.

SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS

Both the 3.3-V and 5-V VCC MACH 4 devices are safe for mixed supply voltage system designs.

The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they

accept inputs from other 3.3-V devices. The 3.3-V device will accept inputs up to 5.5 V. Both the

5-V and 3.3-V versions have the same high-speed performance and provide easy-to-use mixed-

voltage design capability.

BUS-FRIENDLY INPUTS AND I/OS

All MACH 4 devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating

two inverters in series which loop back to the input. This double inversion weakly holds the

input at its last driven logic state. While it is good design practice to tie unused pins to a known

state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where

noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a

logic level “1.” For the circuit diagram, please refer to the document entitled MACH Endurance

Characteristics on the Lattice/Vantis Data Book CD-ROM or Lattice web site.

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MACH 4 Family

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