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M4-32/32-14JI View Datasheet(PDF) - Lattice Semiconductor

Part NameM4-32/32-14JI Lattice
Lattice Semiconductor Lattice
DescriptionHigh-performance E2CMOS in-system programmable logic, 5-V VCC, 32 macrocells, 32 I/Os, 12ns
M4-32/32-14JI Datasheet PDF : 62 Pages
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FUNCTIONAL DESCRIPTION
The fundamental architecture of MACH 4 devices (Figure 1) consists of multiple optimized PAL®
blocks interconnected by a central switch matrix. The central switch matrix allows
communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL
blocks and central switch matrix allow the logic designer to create large designs in a single
device instead of having to use multiple devices.
The key to being able to make effective use of these devices lies in the interconnect schemes.
In MACH 4 architecture, the macrocells have been decoupled from the product terms through
the logic allocator, and the I/O pins have been decoupled from the macrocells due to the output
switch matrix. In addition, more input routing options are provided by the input switch matrix.
These resources provide the flexibility needed to fit designs efficiently.
Clock/Input
Pins
Note 3
Dedicated
Input Pins
Clock
Generator
33/
34/
36
Logic
Array
Input
Switch
Matrix
PAL Block
4
Note 2
Logic 16 Output/ 16
Allocator
Buried
with XOR
Macrocells
16
PAL Block
8
Note 1
16
I/O
Pins
I/O
Pins
PAL Block
Figure 1. MACH 4 Block Diagram and PAL Block Structure
I/O
Pins
17466G-001
Notes:
1. 16 for MACH 4 and MACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page).
2. Block clocks do not go to I/O cells in M4(LV)-32/32 or M4A(3,5)-32/32.
3. M4(LV)-192/96, M4(LV)-256/128, M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which
cannot be used as inputs and do not connect to the central switch matrix.
8
MACH 4 Family
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FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    - Excellent First-Time-FitTM and refit feature
    - SpeedLocking performance for guaranteed fixed timing
    - Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
    - 7.5ns tPD Commercial and 10ns tPD Industrial
    - 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
    - D/T registers and latches
    - Synchronous or asynchronous mode
    - Dedicated input registers
    - Programmable polarity
    - Reset/ preset swapping

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