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M4-32/32-14JI View Datasheet(PDF) - Lattice Semiconductor

Part NameM4-32/32-14JI Lattice
Lattice Semiconductor Lattice
DescriptionHigh-performance E2CMOS in-system programmable logic, 5-V VCC, 32 macrocells, 32 I/Os, 12ns
M4-32/32-14JI Datasheet PDF : 62 Pages
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44-PIN TQFP CONNECTION DIAGRAM (M4(LV)-32/32, M4A(3,5)-32/32,
M4(LV)-64/32 AND M4A(3,5)-64/32)
Top View
44-Pin TQFP
M4(LV)-64/32
M4A(3,5)-64/32
M4(LV)-64/32
M4A(3,5)-64/32
A2
A1
A0
M4(LV)-32/32
M4A(3,5)-32/32
A8
A9
A10
A11
A2 I/O5
1
A1 I/O6
2
A0 I/O7
3
TDI
4
CLK0/I0
5
GND
6
TCK
7
B0 I/O8
8
B1 I/O9
9
B2 I/O10
10
B3 I/O11
11
33
I/O27 D3
32
I/O26 D2
31
I/O25 D1
30
I/O24 D0
29
TDO
28
GND
27
CLK1/I1
26
TMS
25
I/O23 C0
24
I/O22 C1
23
I/O21 C2
B3
B2
B1
B0
M4(LV)-32/32
M4A(3,5)-32/32
B8
B9
B10
M4(LV)-64/32
M4A(3,5)-64/32
M4(LV)-64/32
M4A(3,5)-64/32
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I/O = Input/Output
VCC = Supply Voltage
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
C7
I/O Cell (0-7)
PAL Block (A-D)
MACH 4 Family
49
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FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    - Excellent First-Time-FitTM and refit feature
    - SpeedLocking performance for guaranteed fixed timing
    - Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
    - 7.5ns tPD Commercial and 10ns tPD Industrial
    - 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
    - D/T registers and latches
    - Synchronous or asynchronous mode
    - Dedicated input registers
    - Programmable polarity
    - Reset/ preset swapping

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