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M4-32/32-14JI View Datasheet(PDF) - Lattice Semiconductor

Part NameM4-32/32-14JI Lattice
Lattice Semiconductor Lattice
DescriptionHigh-performance E2CMOS in-system programmable logic, 5-V VCC, 32 macrocells, 32 I/Os, 12ns
M4-32/32-14JI Datasheet PDF : 62 Pages
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MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-5
-55
-6
-65
-7
-10
-12
-14
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
tWIRH
Input register clock width
high
3.0
3.0
3.5
3.5
4.0
5.0
6.0
6.0
ns
tWIL Input latch gate width
4.0
4.0
4.5
4.5
5.0
5.0
6.0
6.0
ns
Frequency:
External feedback, D-type,
Min of 1/(tWLS + tWHS) or 143
133
118
118
95.2
87.0
74.1
60.6
MHz
1/(tSS + tCOS)
External feedback, T-type,
Min of 1/(tWLS + tWHS) or 125
125
111
111
87.0
80.0
69.0
57.1
MHz
1/(tSST + tCOS)
Internal feedback (fCNT),
fMAXS D-type, Min of 1/(tWLS + 182
167
154
154
125
100
83.3
74.1
MHz
tWHS) or 1/(tSS + tCOSi)
Internal feedback (fCNT),
T-type, Min of 1/(tWLS + 154
154
143
143
111
105
87.0
69.0
MHz
tWHS) or 1/(tSST + tCOSi)
No feedback2, Min of 1/
(tWLS + tWHS), 1/(tSS + tHS) 250
250
200
200
154
125
100
83.3
MHz
or 1/(tSST + tHS)
External feedback, D-type,
Min of 1/(tWLA + tWHA) or 111
111
100
100
83.3
66.7
55.6
43.5
MHz
1/(tSA + tCOA)
External feedback, T-type,
Min of 1/(tWLA + tWHA) or 105
105
95.2
95.2
76.9
62.5
52.6
41.7
MHz
1/(tSAT + tCOA)
Internal feedback (fCNTA),
fMAXA D-type, Min of 1/(tWLA + 133
133
125
125
105
83.3
66.7
50.0
MHz
tWHA) or 1/(tSA + tCOAi)
Internal feedback (fCNTA),
T-type, Min of 1/(tWLA + 125
125
118
118
95.2
76.9
62.5
47.6
MHz
tWHA) or 1/(tSAT + tCOAi)
No feedback2, Min of 1/
(tWLA + tWHA), 1/(tSA + 167
167
143
143
125
100
62.5
55.6
MHz
tHA) or 1/(tSAT + tHA)
Maximum input register
fMAXI
frequency, Min of 1/(tWIRH 167
+ tWIRL) or 1/(tSIRS +
167
143
143
125
100
83.3
83.3
MHz
tHIRS)
Notes:
1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book.
2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
MACH 4 Family
45
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FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    - Excellent First-Time-FitTM and refit feature
    - SpeedLocking performance for guaranteed fixed timing
    - Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
    - 7.5ns tPD Commercial and 10ns tPD Industrial
    - 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
    - D/T registers and latches
    - Synchronous or asynchronous mode
    - Dedicated input registers
    - Programmable polarity
    - Reset/ preset swapping

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