M4-128/32-15JC View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
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M4-128/32-15JC
Lattice Semiconductor
M4-128/32-15JC Datasheet PDF : 62 Pages
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MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-5
-55
-6
-65
-7
-10
-12
-14
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
tHA
Asynchronous clock hold
time
2.5
2.5
3.0
3.0
3.5
4.0
5.0
8.0
ns
tCOSi
Synchronous clock to
internal output
2.5
2.5
2.5
2.5
2.5
2.5
3.5
3.5 ns
tCOS
Synchronous clock to
output
4.0
4.0
4.5
4.5
5.0
5.5
6.5
6.5 ns
Asynchronous clock to
tCOAi internal output
5.0
5.0
5.0
5.0
6.0
8.0
10.0
12.0 ns
Asynchronous clock to
tCOA output
6.5
6.5
7.0
7.0
8.5
11.0
13.0
15.0 ns
Latched Delays:
Synchronous latch setup
tSSL time
4.0
4.0
4.5
4.5
6.0
7.0
8.0
10.0
ns
Asynchronous latch setup
tSAL time
3.0
3.0
3.5
3.5
4.0
4.0
5.0
8.0
ns
tHSL
Synchronous latch hold
time
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
tHAL
Asynchronous latch hold
time
3.0
3.0
3.5
3.5
4.0
4.0
5.0
8.0
ns
tPDLi
Transparent latch to
internal output
5.5
5.5
6.0
6.0
7.5
9.0
11.0
12.0 ns
Propagation delay through
tPDL transparent latch to output
7.0
7.0
8.0
8.0
10.0
12.0
14.0
15.0 ns
Synchronous gate to
tGOSi internal output
3.0
3.0
3.0
3.0
3.5
4.5
7.0
8.0 ns
tGOS Synchronous gate to output
4.5
4.5
5.0
5.0
6.0
7.5
10.0
11.0 ns
Asynchronous gate to
tGOAi internal output
6.0
6.0
6.0
6.0
8.5
10.0
13.0
15.0 ns
Asynchronous gate to
tGOA output
7.5
7.5
8.0
8.0
11.0
13.0
16.0
18.0 ns
Input Register Delays:
tSIRS Input register setup time 1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
ns
tHIRS Input register hold time 2.5
2.5
3.0
3.0
3.0
3.0
3.0
4.0
ns
tICOSi
Input register clock to
internal feedback
3.0
3.0
3.0
3.0
3.5
4.5
6.0
6.0 ns
Input Latch Delays:
tSIL Input latch setup time
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
ns
tHIL Input latch hold time
2.5
2.5
3.0
3.0
3.0
3.0
3.0
4.0
ns
tIGOSi
Input latch gate to internal
feedback
3.5
3.5
4.0
4.0
4.0
4.0
4.0
5.0 ns
tPDILi
Transparent input latch to
internal feedback
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0 ns
MACH 4 Family
43
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