M4-96 View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
View to exact match
M4-96
Lattice Semiconductor
M4-96 Datasheet PDF : 62 Pages
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MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-7
-10
-12
-14
-15
-18
Min Max Min Max Min Max Min Max Min Max Min Max Unit
Input Latch Delays with ZHT Option:
tSILZ Input latch setup time - ZHT
tHILZ Input latch hold time - ZHT
tPDILZi Transparent input latch to internal feedback - ZHT
Output Delays:
6.0
6.0
6.0
6.0
6.0
6.0
ns
0.0
0.0
0.0
0.0
0.0
0.0
ns
6.0
6.0
6.0
6.0
6.0
6.0 ns
tBUF Output buffer delay
tSLW Slow slew rate delay adder
tEA Output enable time
tER Output disable time
Power Delay:
2.0
2.0
2.0
2.0
2.0
2.0 ns
2.5
2.5
2.5
2.5
2.5
2.5 ns
9.5
10.0
12.0
15.0
15.0
17.0 ns
9.5
10.0
12.0
15.0
15.0
17.0 ns
tPL Power-down mode delay adder
Reset and Preset Delays:
2.5
2.5
2.5
2.5
2.5
2.5 ns
tSRi Asynchronous reset or preset to internal register output
10.0
12.0
14.0
18.0
18.0
20.0 ns
tSR Asynchronous reset or preset to register output
12.0
14.0
16.0
20.0
20.0
22.0 ns
tSRR Asynchronous reset and preset register recovery time 8.0
8.0
10.0
15.0
15.0
17.0
ns
tSRW Asynchronous reset or preset width
10.0
10.0
12.0
15.0
15.0
17.0
ns
Clock/LE Width:
tWLS Global clock width low
3.0
5.0
6.0
6.0
6.0
7.0
ns
tWHS Global clock width high
3.0
5.0
6.0
6.0
6.0
7.0
ns
tWLA Product term clock width low
4.0
5.0
8.0
9.0
9.0
10.0
ns
tWHA Product term clock width high
4.0
5.0
8.0
9.0
9.0
10.0
ns
tGWS
Global gate width low (for low transparent) or high
(for high transparent)
5.0
5.0
6.0
6.0
6.0
7.0
ns
Product term gate width low (for low transparent) or
tGWA high (for high transparent)
4.0
5.0
6.0
9.0
9.0
11.0
ns
tWIRL Input register clock width low
tWIRH Input register clock width high
tWIL Input latch gate width
4.5
5.0
6.0
6.0
6.0
7.0
ns
4.5
5.0
6.0
6.0
6.0
7.0
ns
5.0
5.0
6.0
6.0
6.0
7.0
ns
41
MACH 4 Family
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