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M4-32/32-14JI View Datasheet(PDF) - Lattice Semiconductor

Part NameM4-32/32-14JI Lattice
Lattice Semiconductor Lattice
DescriptionHigh-performance E2CMOS in-system programmable logic, 5-V VCC, 32 macrocells, 32 I/Os, 12ns
M4-32/32-14JI Datasheet PDF : 62 Pages
First Prev 31 32 33 34 35 36 37 38 39 40 Next Last
MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1
Combinatorial Delay:
tPDi Internal combinatorial propagation delay
tPD Combinatorial propagation delay
Registered Delays:
tSS Synchronous clock setup time, D-type register
tSST Synchronous clock setup time, T-type register
tSA Asynchronous clock setup time, D-type register
tSAT Asynchronous clock setup time, T-type register
tHS Synchronous clock hold time
tHA Asynchronous clock hold time
tCOSi Synchronous clock to internal output
tCOS Synchronous clock to output
tCOAi Asynchronous clock to internal output
tCOA Asynchronous clock to output
Latched Delays:
tSSL Synchronous Latch setup time
tSAL Asynchronous Latch setup time
tHSL Synchronous Latch hold time
tHAL Asynchronous Latch hold time
tPDLi Transparent latch to internal output
tPDL Propagation delay through transparent latch to output
tGOSi Synchronous Gate to internal output
tGOS Synchronous Gate to output
tGOAi Asynchronous Gate to internal output
tGOA Asynchronous Gate to output
Input Register Delays:
tSIRS Input register setup time
tHIRS Input register hold time
tICOSi Input register clock to internal feedback
Input Latch Delays:
tSIL Input latch setup time
tHIL Input latch hold time
tIGOSi Input latch gate to internal feedback
tPDILi Transparent input latch to internal feedback
Input Register Delays with ZHT Option:
tSIRZ Input register setup time - ZHT
tHIRZ Input register hold time - ZHT
-7
-10
-12
-14
-15
-18
Min Max Min Max Min Max Min Max Min Max Min Max Unit
5.5
8.0
10.0
12.0
13.0
16.0 ns
7.5
10.0
12.0
14.0
15.0
18.0 ns
5.5
6.0
7.0
10.0
10.0
12.0
ns
6.5
7.0
8.0
11.0
11.0
13.0
ns
3.5
4.0
5.0
8.0
8.0
10.0
ns
4.5
5.0
6.0
9.0
9.0
11.0
ns
0.0
0.0
0.0
0.0
0.0
0.0
ns
3.5
4.0
5.0
8.0
8.0
10.0
ns
3.5
4.5
6.0
8.0
8.0
10.0 ns
5.5
6.5
8.0
10.0
10.0
12.0 ns
7.5
10.0
12.0
16.0
16.0
18.0 ns
9.5
12.0
14.0
18.0
18.0
20.0 ns
6.0
7.0
8.0
10.0
10.0
12.0
ns
4.0
4.0
5.0
8.0
8.0
10.0
ns
0.0
0.0
0.0
0.0
0.0
0.0
ns
4.0
4.0
5.0
8.0
8.0
10.0
ns
8.0
10.0
12.0
15.0
15.0
18.0 ns
10.0
12.0
14.0
17.0
17.0
20.0 ns
4.0
5.5
8.0
9.0
9.0
10.0 ns
6.0
7.5
10.0
11.0
11.0
12.0 ns
9.0
11.0
14.0
17.0
17.0
20.0 ns
11.0
13.0
16.0
19.0
19.0
22.0 ns
2.0
2.0
2.0
2.0
2.0
2.0
ns
3.0
3.0
3.0
4.0
4.0
4.0
ns
3.5
4.5
6.0
6.0
6.0
6.0 ns
2.0
2.0
2.0
2.0
2.0
2.0
ns
3.0
3.0
3.0
4.0
4.0
4.0
ns
4.0
4.0
4.0
5.0
5.0
6.0 ns
2.0
2.0
2.0
2.0
2.0
2.0 ns
6.0
6.0
6.0
6.0
6.0
6.0
ns
0.0
0.0
0.0
0.0
0.0
0.0
ns
MACH 4 Family
40
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FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    - Excellent First-Time-FitTM and refit feature
    - SpeedLocking performance for guaranteed fixed timing
    - Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
    - 7.5ns tPD Commercial and 10ns tPD Industrial
    - 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
    - D/T registers and latches
    - Synchronous or asynchronous mode
    - Dedicated input registers
    - Programmable polarity
    - Reset/ preset swapping

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