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M4-32/32-14JI View Datasheet(PDF) - Lattice Semiconductor

Part NameM4-32/32-14JI Lattice
Lattice Semiconductor Lattice
DescriptionHigh-performance E2CMOS in-system programmable logic, 5-V VCC, 32 macrocells, 32 I/Os, 12ns
M4-32/32-14JI Datasheet PDF : 62 Pages
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BLOCK DIAGRAM – M4(LV)-192/96 AND M4A(3,5)-192/96
Block B
I/O8I/O15
Block A
I/O0I/O7
CLK0CLK3
Block L
I/O88I/O95
Block K
I/O80I/O87
8
I/O Cells
8
4
Output Switch
Matrix
8
16
16
4
16 Macrocells
16
68 X 90
AND Logic Array
4
and Logic Allocator
24
34
8
I/O Cells
8
4
Output Switch
Matrix
8
16
16
4
16 Macrocells
16
68 X 90
4
AND Logic Array
and Logic Allocator
24
34
4
4
8
I/O Cells
4
8
Output Switch
8
Matrix
16
4
16
Macrocells
16
16
4
68 X 90
AND Logic Array
and Logic Allocator
34
24
8
I/O Cells
4
8
Output Switch
8
Matrix
16
4
16
Macrocells 16
16
4
68 X 90
AND Logic Array
and Logic Allocator
34
24
Block C I/O16I/O23
Block D I/O24I/O31
8
I/O Cells
8
4
Output Switch
Matrix
8
16
16
4
16 Macrocells
16
68 X 90
AND Logic Array
4
and Logic Allocator
24
34
8
I/O Cells
8
4
Output Switch
Matrix
8
16
16
4
16 Macrocells
16
68 X 90
AND Logic Array
4
and Logic Allocator
24
34
8
I/O Cells
4
8
Output Switch
8
Matrix
16
4
16
Macrocells
16
16
68 X 90
4
AND Logic Array
and Logic Allocator
34
24
8
I/O Cells
4
8
Output Switch
8
Matrix
16
4
16
Macrocells 16
16
68 X 90
4
AND Logic Array
and Logic Allocator
34
24
I/O72I/O79 Block J
I/O64I/O71 Block I
34
24
68 X 90
AND Logic Array
and Logic Allocator
4
16
Macrocells
16
16
4
16
Output Switch 8
Matrix
8
4
I/O Cells
8
34
24
68 X 90
AND Logic Array
and Logic Allocator
4
16
Macrocells
16
16
4
16
Output Switch 8
Matrix
8
4
I/O Cells
8
16
34
24
68 X 90
AND Logic Array
4
and Logic Allocator
16
Macrocells
16
4
16
16
8 Output Switch
Matrix
4
8
I/O Cells
8
34
24
68 X 90
AND Logic Array
4
and Logic Allocator
16
Macrocells
16
4
16
16
8 Output Switch
Matrix
4
8
I/O Cells
8
I/O32I/O39
Block E
I/O40I/O47
Block F
I0I15
I/O48I/O55
Block G
I/O56I/O63
Block H
MACH 4 Family
17466G-064
34
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FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    - Excellent First-Time-FitTM and refit feature
    - SpeedLocking performance for guaranteed fixed timing
    - Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
    - 7.5ns tPD Commercial and 10ns tPD Industrial
    - 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
    - D/T registers and latches
    - Synchronous or asynchronous mode
    - Dedicated input registers
    - Programmable polarity
    - Reset/ preset swapping

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