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M4-32/32-14JI View Datasheet(PDF) - Lattice Semiconductor

Part NameM4-32/32-14JI Lattice
Lattice Semiconductor Lattice
DescriptionHigh-performance E2CMOS in-system programmable logic, 5-V VCC, 32 macrocells, 32 I/Os, 12ns
M4-32/32-14JI Datasheet PDF : 62 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
CLK0/I0 CLK0/I1
16
CLOCK
GENERATOR
2
0
C0 M0
M1
C1
MACROCELL
MACROCELL
M0
O0
M1
O1
I/O
CELL
I/O
CELL
C2 M2
C3 M3
MACROCELL
MACROCELL
M2
O2
M3
O3
I/O
CELL
I/O
CELL
C4 M4
C5 M5
MACROCELL
MACROCELL
M4
O4
M5
O5
I/O
CELL
I/O
CELL
C6 M6
C7 M7
MACROCELL
MACROCELL
M6
O6
M7
O7
I/O
CELL
I/O
CELL
C8 M8
C0 M9
C0 M10
C0 M11
MACROCELL
MACROCELL
M8
O8
M9
O9
MACROCELL
MACROCELL
M10
O10
M11
O11
I/O
CELL
I/O
CELL
I/O
CELL
I/O
CELL
C0 M12
C0 M13
MACROCELL
MACROCELL
M12
O12
M13
O13
I/O
CELL
I/O
CELL
97
17
32
INPUT
SWITCH
MATRIX
C0 M14
C0 M15
MACROCELL
MACROCELL
M14
O14
M15
O15
16
16
Figure 18. PAL Block for M4(LV)-32/32 and M4A (3,5)-32/32
I/O
CELL
I/O
CELL
MACH 4 Family
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
17466H-042
29
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FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    - Excellent First-Time-FitTM and refit feature
    - SpeedLocking performance for guaranteed fixed timing
    - Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
    - 7.5ns tPD Commercial and 10ns tPD Industrial
    - 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
    - D/T registers and latches
    - Synchronous or asynchronous mode
    - Dedicated input registers
    - Programmable polarity
    - Reset/ preset swapping

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