|M4-32/32-14JI||High-performance E2CMOS in-system programmable logic, 5-V VCC, 32 macrocells, 32 I/Os, 12ns|
|M4-32/32-14JI Datasheet PDF : 62 Pages |
logic level “1.” For the circuit diagram, please refer to the Input/Output Equivalent Schematics
(page 393) in the General Information Section of the Vantis 1999 Data Book.
All MACH 4A devices have a programmable bit that conﬁgures all inputs and I/Os with either
pull-up or Bus-Friendly characteristics. If the device is conﬁgured in pull-up mode, all inputs
and I/O pins are weakly pulled up. For the circuit diagram, please refer to the Input/Output
Equivalent Schematics (page 393) in the General Information Section of the Vantis 1999 Data
Each individual PAL block in MACH 4 devices features a programmable low-power mode, which
results in power savings of up to 50%. The signal speed paths in the low-power PAL block will
be slower than those in the non-low-power PAL block. This feature allows speed critical paths
to run at maximum frequency while the rest of the signal paths operate in the low-power mode.
PROGRAMMABLE SLEW RATE
Each MACH 4 device I/O has an individually programmable output slew rate control bit. Each
output can be individually conﬁgured for the higher speed transition (3 V/ns) or for the lower
noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew
rate will introduce fewer reﬂections, less noise, and keep ground bounce to a minimum. For
designs with short traces or well terminated lines, the fast slew rate can be used to achieve the
highest speed. The slew rate is adjusted independent of power.
All ﬂip-ﬂops power up to a known state for predictable system initialization. If a macrocell is
conﬁgured to SET on a signal from the control generator, then that macrocell will be SET during
device power-up. If a macrocell is conﬁgured to RESET on a signal from the control generator
or is not conﬁgured for set/reset, then that macrocell will RESET on power-up. To guarantee
initialization values, the VCC rise must be monotonic, and the clock must be inactive until the
reset delay time has elapsed.
A programmable security bit is provided on the MACH 4 devices as a deterrent to unauthorized
copying of the array conﬁguration patterns. Once programmed, this bit defeats readback of the
programmed pattern by a device programmer, securing proprietary designs from competitors.
Programming and veriﬁcation are also defeated by the security bit. The bit can only be reset by
erasing the entire device.
MACH 4A devices are well-suited for those applications that require hot socketing capability.
Hot socketing a device requires that the device, when powered down, can tolerate active signals
on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the
powered-down MACH devices be minimal on active signals.
MACH 4 Family
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