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M4-32/32-14JI View Datasheet(PDF) - Lattice Semiconductor

Part NameDescriptionManufacturer
M4-32/32-14JI High-performance E2CMOS in-system programmable logic, 5-V VCC, 32 macrocells, 32 I/Os, 12ns Lattice
Lattice Semiconductor Lattice
M4-32/32-14JI Datasheet PDF : 62 Pages
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MACH 4 TIMING MODEL
The primary focus of the MACH 4 timing model is to accurately represent the timing in a MACH
4 device, and at the same time, be easy to understand. This model accurately describes all
combinatorial and registered paths through the device, making a distinction between internal
feedback and external feedback. A signal uses internal feedback when it is fed back into the
switch matrix or block without having to go through the output buffer. The input register
specifications are also reported as internal feedback. When a signal is fed back into the switch
matrix after having gone through the output buffer, it is using external feedback.
The parameter, tBUF, is defined as the time it takes to go from feedback through the output buffer
to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter
designator is followed by an “i”. By adding tBUF to this internal parameter, the external parameter
is derived. For example, tPD = tPDi + tBUF. A diagram representing the modularized MACH 4
timing model is shown in Figure 15. Refer to the Technical Note entitled MACH 4 Timing and
High Speed Design for a more detailed discussion about the timing parameters.
IN
BLK CLK
Central
Switch
Matrix
INPUT REG/
INPUT LATCH
tSIRS
tHIRS
tSIL
tHIL
tSIRZ
tHIRZ
tSILZ
tHILZ
tPDILi Q
tICOSi
tIGOSi
tPDILZi
(External Feedback)
(Internal Feedback)
COMB/DFF/TFF/
LATCH/SR*/JK*
*emulated
tSS(T)
tPDi
Q
tSA(T)
tPDLi
tH(S/A)
tCO(S/A)i
tS(S/A)L tGO(S/A)i
tPL
tH(S/A)L tSRi
tSRR
S/R
Figure 15. MACH 4 Timing Model
tBUF
tSLW
OUT
tEA
tER
17466G-025
SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The MACH 4 architecture allows allocation of up to 20 product terms to an individual macrocell
with the assistance of an XOR gate without incurring additional timing delays.
The design of the switch matrix and PAL blocks guarantee a fixed pin-to-pin delay that is
independent of the logic required by the design. Other non-Vantis CPLDs incur serious timing
delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and
SpeedLocking combine to give designs easy access to the performance required in today’s
designs.
24
MACH 4 Family
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