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M4-32/32-14JI View Datasheet(PDF) - Lattice Semiconductor

Part NameDescriptionManufacturer
M4-32/32-14JI High-performance E2CMOS in-system programmable logic, 5-V VCC, 32 macrocells, 32 I/Os, 12ns Lattice
Lattice Semiconductor Lattice
M4-32/32-14JI Datasheet PDF : 62 Pages
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From Input Cell
17466G-002
Figure 12. MACH 4 and MACH 4A with 2:1
Macrocell-I/O Cell Ratio - Input Switch Matrix
17466G-003
Figure 13. MACH 4 and MACH 4A with 1:1
Macrocell-I/O Cell Ratio - Input Switch Matrix
PAL Block Clock Generation
Each MACH 4 device has four clock pins that can also be used as inputs. These pins drive a
clock generator in each PAL block (Figure 14). The clock generator provides four clock signals
that can be used anywhere in the PAL block. These four PAL block clock signals can consist of
a large number of combinations of the true and complement edges of the global clock signals.
Table 17 lists the possible combinations.
GCLK0
GCLK1
GCLK2
GCLK3
Block CLK0
(GCLK0 or GCLK1)
Block CLK1
(GCLK1 or GCLK0)
Block CLK2
(GCLK2 or GCLK3)
Block CLK3
(GCLK3 or GCLK2)
Figure 14. PAL Block Clock Generator 1
17466G-004
Note:
1. M4(LV)-32/32, M4A(3,5)-32/32, M4(LV)-64/32 and M4A(3,5)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied
to GCLK0, and GCLK3 is tied to GCLK1.
22
MACH 4 Family
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