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M4-32/32-14JI View Datasheet(PDF) - Lattice Semiconductor

Part NameM4-32/32-14JI Lattice
Lattice Semiconductor Lattice
DescriptionHigh-performance E2CMOS in-system programmable logic, 5-V VCC, 32 macrocells, 32 I/Os, 12ns
M4-32/32-14JI Datasheet PDF : 62 Pages
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Table 16. Output Switch Matrix Combinations for M4(LV)-32/32 and M4A(3,5)-32/32
Macrocell
Routable to I/O Cells
M0, M1, M2, M3, M4, M5, M6, M7
I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7
M8, M9, M10, M11, M12, M13, M14, M15
I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15
I/O Cell
I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7
I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15
Available Macrocells
M0, M1, M2, M3, M4, M5, M6, M7
M8, M9, M10, M11, M12, M13, M14, M15
20
MACH 4 Family
Direct download click here
 

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    - Excellent First-Time-FitTM and refit feature
    - SpeedLocking performance for guaranteed fixed timing
    - Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
    - 7.5ns tPD Commercial and 10ns tPD Industrial
    - 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
    - D/T registers and latches
    - Synchronous or asynchronous mode
    - Dedicated input registers
    - Programmable polarity
    - Reset/ preset swapping

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