datasheetbank_Logo    Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :

M4-32/32-14JI View Datasheet(PDF) - Lattice Semiconductor

Part NameM4-32/32-14JI Lattice
Lattice Semiconductor Lattice
DescriptionHigh-performance E2CMOS in-system programmable logic, 5-V VCC, 32 macrocells, 32 I/Os, 12ns
M4-32/32-14JI Datasheet PDF : 62 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged,
providing flexibility. In asynchronous mode (Figure 8), a single individual product term is
provided for initialization. It can be selected to control reset or preset.
Power-Up
Reset
Power-Up
Preset
Individual
Reset
Product Term
Individual
Preset
Product Term
AP AR
D/L/T Q
AP AR
D/L/T Q
a. Reset
b. Preset
17466G-014
Figure 8. Asynchronous Mode Initialization Configurations
17466G-015
Note that the reset/preset swapping selection feature effects power-up reset as well. The
initialization functionality of the flip-flops is illustrated in Table 13. The macrocell sends its data
to the output switch matrix and the input switch matrix. The output switch matrix can route this
data to an output if so desired. The input switch matrix can send the signal back to the central
switch matrix as feedback.
Table 13. Asynchronous Reset/Preset Operation
AR
AP
CLK/LE1
Q+
0
0
X
See Table 12
0
1
X
1
1
0
X
0
1
1
X
0
Note:
1. Transparent latch is unaffected by AR, AP
Output Switch Matrix
The output switch matrix allows macrocells to be connected to any of several I/O cells within a
PAL block. This provides high flexibility in determining pinout and allows design changes to
occur without effecting pinout.
In MACH 4 and MACH 4A devices with 2:1 Macrocell-I/O cell ratio, each PAL block has twice as
many macrocells as I/O cells. The MACH 4 output switch matrix allows for half of the macrocells
to drive I/O cells within a PAL block, in combinations according to Figure 9. Each I/O cell can
choose from eight macrocells; each macrocell has a choice of four I/O cells. The MACH 4 and
MACH 4A devices with 1:1 Macrocell-I/O cell ratio allow each macrocell to drive one of eight I/
O cells (Figure 9).
MACH 4 Family
17
Direct download click here
 

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    - Excellent First-Time-FitTM and refit feature
    - SpeedLocking performance for guaranteed fixed timing
    - Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
    - 7.5ns tPD Commercial and 10ns tPD Industrial
    - 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
    - D/T registers and latches
    - Synchronous or asynchronous mode
    - Dedicated input registers
    - Programmable polarity
    - Reset/ preset swapping

Share Link : Lattice
@ 2014 - 2018  [ Home ] [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]