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AD260AND-5 View Datasheet(PDF) - Analog Devices

Part Name
Description
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AD260AND-5 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
AD260–SPECIFICATIONS (Typical at TA = +25؇C, +5 V dcSYS, +5 V dcFLD, tRR = 50 ns max unless otherwise noted)
Parameter
Conditions
Min Typ Max
Units
INPUT CHARACTERISTICS
Threshold Voltage
Positive Transition (VT+)
Negative Transition (VT–)
Hysteresis Voltage (VH)
Input Capacitance (CIN)
Input Bias Current (IIN)
OUTPUT CHARACTERISTICS
Output Voltage1
High Level (VOH)
Low Level (VOL)
Output Three-State Leakage Current
DYNAMIC RESPONSE 1 (Refer to Figure 2)
Max Logic Signal Frequency (fMIN)
Waveform Edge Symmetry Error (tERROR)
Logic Edge Propagation Delay (tPHL, tPLH)
Minimum Pulsewidth (tPWMIN)
Max Output Update Delay on Fault or After
Power-Up Reset Interval (30 µs)2
ISOLATION BARRIER RATING3
Operating Isolation Voltage (VCMV)
Isolation Rating Test Voltage (VCMV TEST)4
Transient Immunity (VTRANSIENT)
Isolation Mode Capacitance (CISO)
Capacitive Leakage Current (ILEAD)
POWER TRANSFORMER
Primary Winding
Inductance (LP)
Number of Turns (NP)
Resistance
Max Volt-Seconds (E × t)
Recommended Operating Frequency
Absolute Min Operating Frequency
Secondary Winding
Number of Turns (NS)
Resistance
Insulation Withstand (VCMV TEST)
Capacitance
Recommended Max Power
+5 V dcSYS = 4.5 V
+5 V dcSYS = 5.5 V
+5 V dcSYS = 4.5 V
+5 V dcSYS = 5.5 V
+5 V dcSYS = 4.5 V
+5 V dcSYS = 5.5 V
Per Input
+5 V dcSYS = 4.5 V, |IO| = 0.02 mA
+5 V dcSYS = 4.5 V, |IO| = 4 mA
+5 V dcSYS = 4.5 V, |IO| = 0.02 mA
+5 V dcSYS = 4.5 V, |IO| = 4 mA
ENABLESYS/FLD @ Logic Low/High Level Respectively
50% Duty Cycle, +5 V dcSYS = 5 V
tPHL vs. tPLH
AD260A
AD260B
AD260A
AD260B
Total Capacitance, All Lines and Transformer
240 V rms @ 60 Hz
Bifilar Wound, Center-Tapped
Each Half
Each Half
Each Half
Each Half
–25°C to +85°C, Push-Pull Drive
–25°C to +85°C, Push-Pull Drive
Bifilar Wound, Center-Tapped
Each Half
Each Half
Primary to Secondary
Primary to Secondary
Rated Performance
2.0 2.7
3.0 3.2
0.9 1.8
1.2 2.2
0.4 0.9
0.5 1.0
5
0.5
4.4
3.7
0.5
20
±1
14
25
12
1750
3500
10,000
14
1
26
0.6
150 200
75
48
2.3
3,500
5
1.0
3.15
4.2
2.2
3.0
1.4
1.5
0.1
0.4
25
375
1250
18
2
27
300
1.5
V
V
V
V
V
V
pF
µA
V
V
V
V
µA
MHz
ns
ns
ns
µs
V rms
V rms
V rms
V rms
V/µs
pF
µA rms
mH
Turns
V × µs
kHz
kHz
Turns
V rms
pF
W
POWER SUPPLY
Supply Voltage (+5 V dcSYS and +5 V dcFLD)
Power Dissipation Capacitance
Quiescent Supply Current
Supply Current
Rated Performance
Operating
Effective, per Input, Either Side
Effective per Output, Either Side—No Load
Each, +5 V dcSYS & FLD
All Lines @ 10 MHz (Sum of +5 V dcSYS & FLD)
4.5
5.5
V dc
4.0
5.75
V dc
8
pF
28
pF
4
mA
18
mA
TEMPERATURE RANGE
Rated Performance (TA)5
Storage (TSTG)
–25
+85
°C
–40
+85
°C
NOTES
1For best performance, bypass +5 V dc supplies to com. at or near the device (0.01 µF). +5 V dc supplies are also internally bypassed with 0.05 µF.
2As the supply voltage is applied to either side of the AD260, the internal circuitry will go into a power-up reset mode (all lines disabled) for about 30 µs after the point where
+5 V dcSYS & FLD passes above 3.3 V.
3“Operating” isolation voltage is derived from the Isolation Test Voltage in accordance with such methods as found in VDE-0883 wherein a device will be “hi-pot” tested at twice
the operating voltage, plus one thousand volts. Partial discharge testing, with an acceptance threshold of 80 pC of discharge may be considered the same as a hi-pot test (but
nondestructive).
4Partial Discharge at 80 pC THLD.
5Supply Current will increase slightly, but otherwise the unit will function within specification to – 40°C.
Specifications are subject to change without notice.
–2–
REV. 0
 

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