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AD9144 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD9144 Quad, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter ADI
Analog Devices ADI
AD9144 Datasheet PDF : 125 Pages
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Data Sheet
AD9144
LATENCY VARIATION SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = 25°C, IOUTFS = 20 mA, unless otherwise noted.
Table 7.
Parameter
DAC LATENCY VARIATION
SYNC On
PLL Off
PLL On
Min
Typ
0
−1
Max
Unit
1
DACCLK cycles
+1
DACCLK cycles
JESD204B INTERFACE ELECTRICAL SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 8.
Parameter
JESD204B DATA INPUTS
Input Leakage Current
Logic High
Logic Low
Unit Interval
Common-Mode Voltage
Differential Voltage
VTT Source Impedance
Differential Impedance
Differential Return Loss
Common-Mode Return Loss
DIFFERENTIAL OUTPUTS (SYNCOUT±)2
Output Differential Voltage
Output Offset Voltage
Output Differential Voltage
DETERMINISTIC LATENCY
Fixed
Variable
SYSREF±-to-LMFC DELAY
Symbol Test Conditions/Comments
Min Typ
UI
VRCM
R_VDIFF
ZTT
ZRDIFF
RLRDIF
RLRCM
25°C
Input level = 1.2 V ± 0.25 V, VTT = 1.2 V
Input level = 0 V
AC-coupled, VTT = SVDD121
At dc
At dc
10
−4
94
−0.05
110
80 100
8
6
VOD
Normal swing mode: Register 0x2A5[0] = 0 192
VOS
1.19
VOD
High swing mode: Register 0x2A5[0] = 1 341
4
Max Unit
µA
µA
714 ps
+1.85 V
1050 mV
30 Ω
120 Ω
dB
dB
235 mV
1.27 V
394 mV
17
PClock3 cycles
2
PClock3 cycles
DAC clock cycles
1 As measured on the input side of the ac coupling capacitor.
2 IEEE Standard 1596.3 LVDS compatible.
3 PClock is the AD9144 internal processing clock and equals the lane rate ÷ 40.
Rev. B | Page 9 of 125
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