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AD9144BCPAZ View Datasheet(PDF) - Analog Devices

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AD9144BCPAZ Datasheet PDF : 125 Pages
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AD9144
Data Sheet
SYSREF TO DAC CLOCK TIMING SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, SYSREF± common-mode voltages = 0.0 V, 0.6 V, 1.25 V, and 2.0 V, unless otherwise noted.
Table 5.
Parameter
Test Conditions/Comments
Min
Typ Max Unit
SYSREF DIFFERENTIAL SWING = 0.4 V, SLEW RATE = 1.3 V/ns
Setup Time
AC-coupled
126
ps
DC-coupled
131
ps
Hold Time
AC-coupled
92
ps
DC-coupled
119
ps
SYSREF DIFFERENTIAL SWING = 0.7 V, SLEW RATE = 2.28 V/ns
Setup Time
AC-coupled
96
ps
DC-coupled
104
ps
Hold Time
AC-coupled
77
ps
DC-coupled
95
ps
SYSREF SWING = 1.0 V, SLEW RATE = 3.26 V/ns
Setup Time
AC-coupled
83
ps
DC-coupled
90
ps
Hold Time
AC-coupled
68
ps
DC-coupled
84
ps
DIGITAL INPUT DATA TIMING SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = 25°C, IOUTFS = 20 mA, unless otherwise noted.
Table 6.
Parameter
LATENCY
Interface
Interpolation
Inverse Sinc
Fine Modulation
Coarse Modulation
fS/8
fS/4
Digital Phase Adjust
Digital Gain Adjust
Power-Up Time
Dual A Only
Dual B Only
All DACs
Test Conditions/Comments
Min
Typ
17
58
137
251
484
17
20
8
4
12
12
Register 0x011 from 0x60 to 0x00
60
Register 0x011 from 0x18 to 0x00
60
Register 0x011 from 0x7C to 0x00
60
Max
Unit
PClock1 cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
µs
µs
µs
1 PClock is the AD9144 internal processing clock and equals the lane rate ÷ 40.
Rev. B | Page 8 of 125
 

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