AD9144BCPZRL View Datasheet(PDF) - Analog Devices
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Description
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AD9144BCPZRL Datasheet PDF : 125 Pages
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AD9144
Data Sheet
DIGITAL SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input Voltage (VIN) Logic
High
Low
CMOS OUTPUT LOGIC LEVEL
Output Voltage (VOUT) Logic
High
Low
MAXIMUM DAC UPDATE RATE1
ADJUSTED DAC UPDATE RATE
INTERFACE4
Number of JESD204B Lanes
JESD204B Serial Interface Speed
Minimum
Maximum
DAC CLOCK INPUT (CLK+, CLK−)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
REFCLK Frequency (PLL Mode)
SYSTEM REFERENCE INPUT
(SYSREF+, SYSREF−)
Differential Peak-to-Peak
Voltage
Common-Mode Voltage
SYSREF± Frequency5
SYSREF TO DAC CLOCK6
Setup Time
Hold Time
Keep Out Window
SPI
Maximum Clock Rate
Minimum SCLK Pulse Width
High
Low
SDIO to SCLK
Setup Time
Hold Time
Symbol
tSSD
tHSD
KOW
SCLK
tPWH
tPWL
tDS
tDH
Test Conditions/Comments
1.8 V ≤ IOVDD ≤ 3.3 V
1.8 V ≤ IOVDD ≤ 3.3 V
1.8 V ≤ IOVDD ≤ 3.3 V
1.8 V ≤ IOVDD ≤ 3.3 V
1× interpolation2 (see Table 4)
2× interpolation3
4× interpolation
8× interpolation
1× interpolation
2× interpolation
4× interpolation
8× interpolation
Per lane
Per lane, SVDD12 = 1.3 V ± 2%
Self biased input, ac-coupled
6.0 GHz ≤ fVCO ≤ 12.0 GHz
SYSREF differential swing = 0.4 V, slew
rate = 1.3 V/ns, common modes tested:
ac-coupled, 0 V, 0.6 V, 1.25 V, 2.0 V
IOVDD = 1.8 V
Min
Typ Max
0.7 × IOVDD
0.3 × IOVDD
0.75 × IOVDD
0.25 × IOVDD
1060
2120
2800
2800
1060
1060
700
350
8
1.44
12.4
400
2800
35
1000 2000
600
1000
400
1000 2000
0
2000
fDATA/(K × S)
131
119
20
10
8
12
5
2
Unit
V
V
V
V
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
Lanes
Gbps
Gbps
mV
mV
MHz
MHz
mV
mV
Hz
ps
ps
ps
MHz
ns
ns
ns
ns
Rev. B | Page 6 of 125
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