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AD9144BCPAZ View Datasheet(PDF) - Analog Devices

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AD9144BCPAZ Datasheet PDF : 125 Pages
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Data Sheet
AD9144
TRANSPORT LAYER
LANE 0 OCTETS
LANE 3 OCTETS
PCLK_0
SPI CONTROL
LANE 4 OCTETS
LANE 7 OCTETS
PCLK_1
SPI CONTROL
TRANSPORT LAYER
(QBD)
DELAY
BUFFER 0
F2S_0
DAC A_I0[15:0]
DAC A_Q0[15:0]
DELAY
BUFFER 1
F2S_1
DAC B_I0[15:0]
DAC B_Q0[15:0]
Figure 52. Transport Layer Block Diagram
The transport layer receives the descrambled JESD204B frames
and converts them to DAC samples based on the programmed
JESD204B parameters shown in Table 44. A number of device
parameters are defined in Table 45.
Table 44. JESD204B Transport Layer Parameters
Parameter Description
F
Number of octets per frame per lane: 1, 2, or 4.
K
Number of frames per multiframe.
K = 32 if F = 1, K = 16 or 32 otherwise.
L
Number of lanes per converter device (per link), as
follows:
1, 2, 4, or 8 (single-link mode).
1, 2, or 4 (dual-link mode).
M
Number of converters per device (per link), as follows:
1, 2, or 4 (single-link mode).
1 or 2 (dual-link mode).
S
Number of samples per converter, per frame: 1 or 2.
Table 45. JESD204B Device Parameters
Parameter Description
CF
Number of control words per device clock per link.
Not supported, must be 0.
CS
Number of control bits per conversion sample.
Not supported, must be 0.
HD
High density user data format. Used when samples
must be split across lanes.
Set to 1 when F = 1, otherwise 0.
N
Converter resolution = 16.
Nʹ (NP)
Total number of bits per sample = 16.
Certain combinations of these parameters, called JESD204B
operating modes, are supported by the AD9144. See Table 46
and Table 47 for a list of supported modes, along with their
associated clock relationships.
Rev. B | Page 47 of 125
 

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