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AD9144BCPAZ View Datasheet(PDF) - Analog Devices

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AD9144BCPAZ Datasheet PDF : 125 Pages
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Data Sheet
AD9144
Lane FIFO
The FIFOs in front of the crossbar switch and deframer
synchronize the samples sent on the high speed serial data
interface with the deframer clock by adjusting the phase of the
incoming data. The FIFO absorbs timing variations between the
data source and the deframer; this allows up to two PClock cycles
of drift from the transmitter. The FIFO_STATUS_REG_0 register
and FIFO_STATUS_REG_1 register (Register 0x30C and
Register 0x30D, respectively) can be monitored to identify
whether the FIFOs are full or empty.
Lane FIFO IRQ
An aggregate lane FIFO error bit is also available as an IRQ
event. Use Register 0x01F[1] to enable the FIFO error bit, and
then use Register 0x023[1] to read back its status and reset the
IRQ signal. See the Interrupt Request Operation section for
more information.
Crossbar Switch
Register 0x308 to Register 0x30B allow arbitrary mapping of
physical lanes (SERDINx±) to logical lanes used by the SERDES
deframers.
Table 41. Crossbar Registers
Address Bits
Logical Lane
0x308
[2:0]
LOGICAL_LANE0_SRC
0x308
[5:3]
LOGICAL_LANE1_SRC
0x309
[2:0]
LOGICAL_LANE2_SRC
0x309
[5:3]
LOGICAL_LANE3_SRC
0x30A
[2:0]
LOGICAL_LANE4_SRC
0x30A
[5:3]
LOGICAL_LANE5_SRC
0x30B
[2:0]
LOGICAL_LANE6_SRC
0x30B
[5:3]
LOGICAL_LANE7_SRC
Write each LOGICAL_LANEy_SRC with the number (x) of the
desired physical lane (SERDINx±) from which to obtain data.
By default, all logical lanes use the corresponding physical lane
as their data source. For example, by default LOGICAL_
LANE0_SRC = 0; therefore, Logical Lane 0 obtains data from
Physical Lane 0 (SERDIN0±). If instead the user wants to use
SERDIN4± as the source for Logical Lane 0, the user must write
LOGICAL_LANE0_SRC = 4.
Lane Inversion
Register 0x334 allows inversion of desired logical lanes, which
can be used to ease routing of the SERDINx± signals. For each
Logical Lane x, set Bit x of Register 0x334 to 1 to invert it.
Deframers
The AD9144 consists of two quad-byte deframers (QBDs). Each
deframer takes in the 8-bit/10-bit encoded data from the
deserializer (via the crossbar switch), decodes it, and descrambles it
into JESD204B frames before passing it to the transport layer to be
converted to DAC samples. The deframer processes four symbols
(or octets) per processing clock (PClock) cycle.
In single-link mode, Deframer 0 is used exclusively and Deframer 1
remains inactive. In dual-link mode, both QBDs are active and
must be configured separately using the LINK_PAGE bit
(Register 0x300[2]) to select which link is being configured. The
LINK_MODE bit (Register 0x300[3]) is 1 for dual-link, or 0 for
single-link.
Each deframer uses the JESD204B parameters that the user has
programmed into the register map to identify how the data has
been packed and how to unpack it. The JESD204B parameters
are discussed in detail in the Transport Layer section; many of
the parameters are also needed in the transport layer to convert
JESD204B frames into samples.
Descrambler
The AD9144 provides an optional descrambler block using a
self synchronous descrambler with a polynomial: 1 + x14 + x15.
Enabling data scrambling reduces spectral peaks that are
produced when the same data octets repeat from frame to
frame. It also makes the spectrum data independent so that
possible frequency-selective effects on the electrical interface do
not cause data-dependent errors. Descrambling of the data is
enabled by setting the SCR bit (Register 0x453[7]) to 1.
Syncing LMFC Signals
The first step in guaranteeing synchronization across links and
devices begins with syncing the LMFC signals. Each DAC dual
(DAC Dual A: DAC0/DAC1 and DAC Dual B: DAC2/DAC3)
has its own LMFC signal. In Subclass 0, the LMFC signals for
each of the two links are synchronized to an internal processing
clock. In Subclass 1, all LMFC signals (for all duals and devices)
are synchronized to an external SYSREF signal. All LMFC sync
registers are paged as described in the Dual Paging section.
SYSREF Signal
The SYSREF signal is a differential source synchronous input
that synchronizes the LMFC signals in both the transmitter
and receiver in a JESD204B Subclass 1 system to achieve
deterministic latency.
The SYSREF signal is an active high signal that is sampled by
the device clock rising edge. It is best practice that the device
clock and SYSREF signals be generated by the same source,
such as the AD9516-1 clock generator, so that the phase
alignment between the signals is fixed. When designing for
optimum deterministic latency operation, consider the timing
distribution skew of the SYSREF signal in a multipoint link
system (multichip).
The AD9144 supports a single pulse or step, or a periodic
SYSREF± signal. The periodicity can be continuous, strobed, or
gapped periodic. The SYSREF± signal can always be dc-coupled
(with a common-mode voltage of 0 V to 2 V). When dc-coupled,
a small amount of common-mode current (<500 µA) is drawn
from the SYSREF± pins. See Figure 45 for the SYSREF± internal
circuit.
Rev. B | Page 41 of 125
 

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