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AD9144BCPZ View Datasheet(PDF) - Analog Devices

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AD9144BCPZ Datasheet PDF : 125 Pages
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Data Sheet
fREF
DivFactor
(1, 2, 4)
BIT RATE ÷ 40
PFD
80MHz
MAX
CHARGE
PUMP
UP
DOWN
C1 C2
C3
R1
R3
VCO
LDO
2.825GHz TO 6.2GHz
OUTPUT
IQ
LC VCO
5.65GHz TO 12.4GHz
÷2
÷80
3.2mA
ALC CAL
FO CAL
CAL CONTROL BITS
Figure 38. SERDES PLL Synthesizer Block Diagram Including VCO Divider Block
AD9144
Clock and Data Recovery
The deserializer is equipped with a CDR circuit. Instead of
recovering the clock from the JESD204B serial lanes, the CDR
recovers the clocks from the SERDES PLL. The 2.825 GHz to
6.2 GHz output from the SERDES PLL, shown in Figure 38,
is the input to the CDR.
A CDR sampling mode must be selected to generate the lane
rate clock inside the device. If the desired lane rate is greater
than 5.65 GHz, half rate CDR operation must be used. If the
desired lane rate is less than 5.65 GHz, disable half rate operation.
If the lane rate is less than 2.825 GHz, disable half rate and
enable 2× oversampling to recover the appropriate lane rate clock.
Table 40 gives a breakdown of CDR sampling settings that must
be set dependent on the LaneRate.
Table 40. CDR Operating Modes
ENHALFRATE,
LaneRate (Gbps) Register 0x230[5]
1.44 to 3.1
0
2.88 to 6.2
0
5.75 to 12.4
1
CDR_OVERSAMP,
Register 0x230[1]
1
0
0
The CDR circuit synchronizes the phase used to sample the data on
each serial lane independently. This independent phase adjustment
per serial interface ensures accurate data sampling and eases the
implementation of multiple serial interfaces on a PCB.
After configuring the CDR circuit, reset it and then release the
reset by writing 1 and then 0 to Register 0x206[0].
Power-Down Unused PHYs
Note that any unused and enabled lanes consume extra power
unnecessarily. Each lane that is not being used (SERDINx±)
must be powered off by writing a 1 to the corresponding bit of
PHY_PD (Register 0x201).
Equalization
To compensate for signal integrity distortions for each PHY
channel due to PCB trace length and impedance, the AD9144
employs an easy to use, low power equalizer on each JESD204B
channel. The AD9144 equalizers can compensate for insertion
losses far greater than required by the JESD204B specification.
The equalizers have two modes of operation that are determined
by the EQ_POWER_MODE register setting in Register 0x268[7:6].
In low power mode (Register 0x268[7:6] = 2b’01) and operating
at the maximum lane rate of 10 Gbps, the equalizer can
compensate for up to 12 dB of insertion loss. In normal mode
(Register 0x268[7:6] = 2b’00), the equalizer can compensate for
up to 17.5 dB of insertion loss. This performance is shown in
Figure 39 as an overlay to the JESD204B specification for
insertion loss. Figure 39 shows the equalization performance at
10.0 Gbps, near the maximum baud rate for the AD9144.
Figure 40 and Figure 41 are provided as points of reference for
hardware designers and show the insertion loss for various
lengths of well laid out stripline and microstrip transmission
lines. See the Hardware Considerations section for specific layout
recommendations for the JESD204B channel.
Low power mode is recommended if the insertion loss of the
JESD204B PCB channels is less than that of the most lossy
supported channel for lower power mode (shown in Figure 39).
If the insertion loss is greater than that, but still less than that of
the most lossy supported channel for normal mode (shown in
Figure 39), use normal mode. At 10 Gbps operation, the EQ in
normal mode consumes about 4 mW more power per lane used
than in low power EQ mode. Note that either mode can be used
in conjunction with transmitter preemphasis to ensure
functionality and/or to optimize for power.
Rev. B | Page 37 of 125
 

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