AD9144 View Datasheet(PDF) - Analog Devices
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AD9144 Datasheet PDF : 125 Pages
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Data Sheet
AD9144
Table 36. Dual-Link JESD204B Operating Modes for Link 0 and Link 1
Parameter
M (Converter Counts)
L (Lane Counts)
S (Samples per Converter per Frame)
F (Octets/Frame per Lane)
Example Clock for 10 Gbps Lane Rate
PClock (MHz)
Frame Clock (MHz)
Sample Clock (MHz)
4
2
4
1
1
250
1000
1000
5
2
4
2
2
250
500
1000
Mode
6
7
2
2
2
1
1
1
2
4
250
250
500
250
500
250
9
10
1
1
2
1
1
1
1
2
250
250
1000
500
1000
500
PHYSICAL LAYER
The physical layer of the JESD204B interface, hereafter referred
to as the deserializer, has eight identical channels. Each channel
consists of the terminators, an equalizer, a clock and data recovery
(CDR) circuit, and the 1:40 demux function (see Figure 36).
DESERIALIZER
SERDINx±
TERMINATION EQUALIZER
CDR
1:40
Table 37. PHY Termination Autocalibration Routine
Address Value Description
0x2AA 0xB7 SERDES interface termination configuration
0x2AB 0x87 SERDES interface termination configuration
0x2B1 0xB7 SERDES interface termination configuration
0x2B2 0x87 SERDES interface termination configuration
0x2A7 0x01 Autotune PHY terminations
0x2AE 0x01 Autotune PHY terminations
SPI
CONTROL
FROM SERDES PLL
Figure 36. Deserializer Block Diagram
JESD204B data is input to the AD9144 via the SERDINx± 1.2 V
differential input pins as per the JESD204B specification.
Interface Power-Up and Input Termination
Before using the JESD204B interface, it must be powered up by
setting Register 0x200[0] = 0. In addition, each physical lane that is
not being used (SERDINx±) must be powered down. To do so,
set the corresponding Bit x for Physical Lane x in Register 0x201 to
0 if the physical lane is being used, and to 1 if it is not being used.
The AD9144 autocalibrates the input termination to 50 Ω.
Before running the termination calibration, Register 0x2AA,
Register 0x2AB, Register 0x2B1, and Register 0x2B2 must be
written as described in Table 37 to guarantee proper calibration.
The termination calibration begins when Register 0x2A7[0] and
Register 0x2AE[0] transition from low to high. Register 0x2A7
controls autocalibration for PHY 0, PHY 1, PHY 6, and PHY 7.
Register 0x2AE controls autocalibration for PHY 2, PHY 3,
PHY 4, and PHY 5.
The PHY termination autocalibration routine is as shown in
Table 37.
The input termination voltage of the DAC is sourced externally
via the VTT pins (Pin 21, Pin 23, Pin 40, and Pin 43). Set VTT by
connecting it to SVDD12. It is recommended that the JESD204B
inputs be ac-coupled to the JESD204B transmit device using
100 nF capacitors.
Receiver Eye Mask
The AD9144 complies with the JESD204B specification
regarding the receiver eye mask and is capable of capturing data
that complies with this mask. Figure 37 shows the receiver eye
mask normalized to the data rate interval with a 600 mV VTT
swing. See the JESD204B specification for more information
regarding the eye mask and permitted receiver eye opening.
LV-OIF-11G-SR RECEIVER EYE MASK
525
55
0
–55
–525
0
0.35 0.5 0.65
1.00
TIME (UI)
Figure 37. Receiver Eye Mask
Rev. B | Page 35 of 125
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